I want to realize an EPP interface using Altera FPGA Cyclone (read and write operation) but I have some synchronization problems. I want to sample datas from a 4 bits chip, storing them in a ZBT SRAM memory (Flow trought) and later acquiring them by parallel port. the chip works at 10MHz but the pll on board can't divide input clock of 20MHz for 2. How can I divide the frequency? thanks. Does anyone do something like that?
Hi Michelle,
I think Cyclone PLL needs xtal input > 15 MHz, also cannot lock on frequencies below 15 MHz.... Also think that 10 MHz for a PC EPP port is rather high, try 1 MHz to start with. You must synchronise PC EPP signals (strobes, wait ) with the Internal Cyclone signals, use the standard 2 flip-flop synchronisers for this. regards
Ron Proveniers
"Michele Bergo" schreef in bericht news:%ORid.18871$ snipped-for-privacy@twister1.libero.it...
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Use a simple counter, in this case a single D-Type Flip Flop.You don't need a PLL if you need sub factors or the main clock.
Victor
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"ron" ha scritto nel messaggio news:418cee87$0$21106$ snipped-for-privacy@news.xsall.nl...
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"Victor Schutte" ha scritto nel messaggio news:cml4l6$7i8$ snipped-for-privacy@ctb-nnrp2.saix.net...
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thank u very much
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