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Endpoint Block Plus v1.5 example design

Hello,

I'm trying to get running the example design coming with Endpoint Block Plus v1.5. I have generated the core with ise's coregen and compiled the smartmodel libs also with with ise. But when starting the simulation the following happens:

ncsim: 06.11-s002: (c) Copyright 1995-2007 Cadence Design Systems, Inc.

***** Registering Synopsys SWIFT PLI tasks *****

Runtime, LMTV v12.33 Copyright (c) 1984-2008 Synopsys Inc. ALL RIGHTS RESERVED Platform Type: linux (32-bit). You can use the Browser tool to configure the SmartModel Library and access information about SmartModels: $LMC_HOME/bin/sl_browser

SmartModel product documentation is available here: $LMC_HOME/doc/smartmodel/manuals/intro.pdf

formatting link

(LMTV) (3027)Error: number of instance pins in Verilog: '1353', does not match swift: '1325'

Note: Model pcie_internal_1_1_swift: Model Vendor: `Xilinx'. SmartModel Instance boardx01.xilinx_pci_exp_1_lane_ep.ep.\BU2/U0/ pcie_ep0/pcie_blk/ pcie_ep .pcie_internal_1_1_swift_1.I1(PCIE_INTERNAL_1_1_SWIFT:pcie_internal_1_1_swift), at time 0.0 ns

Note: Model gt11_swift: Model Vendor: `Xilinx'. SmartModel Instance boardx01.xilinx_pci_exp_1_lane_downstream_port.xilinx_pci_exp_1_lane_dsport.pci_exp_1_lane_64b_dsport.plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.gt11_swift_1.I1(GT11_SWIFT:gt11_swift), at time 0.0 ns ncsim> run Running default test {sample_smoke_test0}...... [ 0] : System Reset Asserted... [ 4995000] : System Reset De-asserted... [ 8522100] : Transaction Reset Is De-asserted...

and then nothing else.

Can someone tell me what I could've done wrong? Perhaps something with the compilation of the libs? Or does someone know what to do with this "(LMTV) (3027)Error"? I can't find anything on this error in the internet or anywhere else.

Thanks in advance. Michael

Reply to
miriemer
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Hello,

I'm trying to get running the example design coming with Endpoint Block Plus v1.5. I have generated the core with ise's coregen and compiled the smartmodel libs also with with ise. But when starting the simulation the following happens:

ncsim: 06.11-s002: (c) Copyright 1995-2007 Cadence Design Systems, Inc.

***** Registering Synopsys SWIFT PLI tasks *****

Runtime, LMTV v12.33 Copyright (c) 1984-2008 Synopsys Inc. ALL RIGHTS RESERVED Platform Type: linux (32-bit). You can use the Browser tool to configure the SmartModel Library and access information about SmartModels: $LMC_HOME/bin/sl_browser

SmartModel product documentation is available here: $LMC_HOME/doc/smartmodel/manuals/intro.pdf

formatting link

(LMTV) (3027)Error: number of instance pins in Verilog: '1353', does not match swift: '1325'

Note: Model pcie_internal_1_1_swift: Model Vendor: `Xilinx'. SmartModel Instance boardx01.xilinx_pci_exp_1_lane_ep.ep.\BU2/U0/ pcie_ep0/pcie_blk/ pcie_ep .pcie_internal_1_1_swift_1.I1(PCIE_INTERNAL_1_1_SWIFT:pcie_internal_1_1_swift), at time 0.0 ns

Note: Model gt11_swift: Model Vendor: `Xilinx'. SmartModel Instance boardx01.xilinx_pci_exp_1_lane_downstream_port.xilinx_pci_exp_1_lane_dsport.pci_exp_1_lane_64b_dsport.plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.gt11_swift_1.I1(GT11_SWIFT:gt11_swift), at time 0.0 ns ncsim> run Running default test {sample_smoke_test0}...... [ 0] : System Reset Asserted... [ 4995000] : System Reset De-asserted... [ 8522100] : Transaction Reset Is De-asserted...

and then nothing else.

Can someone tell me what I could've done wrong? Perhaps something with the compilation of the libs? Or does someone know what to do with this "(LMTV) (3027)Error"? I can't find anything on this error in the internet or anywhere else.

Thanks in advance. Michael

Reply to
miriemer

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