Enabling clock generation

Hi,

I have a PLL in my design. This PLL generates two clocks which are used in my design. Now I want to cut these clocks from the design and generate my own clocks for simulation. The testclocks 'l_sdram_clk' and 'l_sdram_clk_90' are going to run when the PLL is locked so that I use the 'l_pll_locked' signal to enable the generation of the clocks. I try that by using GENERATE. But the simulation shows that 'l_sdram_clk' and 'l_sdram_clk_90' remain undefined.

How can I solve that problem ?

I would appreciate your help.

Rgds André

Here's the code:

architecture xy of zx is

... signal l_pll_locked : std_logic;

-- This signal comes out of the PLL, it gets '1' in the simulation

test_1: if (l_pll_locked='1') generate process begin l_sdram_clk

im not sure why are you doing this this way, but what do you expect to happen when l_pll_locked equals 0 during simulation? (think about it, so that you can understand why it's failing even when it gets 1 assigned) do you expect the process to just "dissapear"?? because in that case you want a process to "appear" when l_pll_locked equals 1. im pretty sure that's not possible.

try to RTFM before (or ask to your coworkers, it's a lot FASTER than usenet!) so that you learn and understand why and how, before doing hit-and-miss coding techniques if you dont want to read the LRM (which is somehow hard to read), get a nice book, P. Ashenden, etc. but hey! im no hardware hotshot either!

hint: try to use gated clocks, im guessing while the pll is not locked it's clock output is 0...

l_sdram_clk test_2: if (l_pll_locked='1') generate