Hi,
I'm a student new to fpga design and am trying to design a board with a spartan-3, 2x(1Mx16) SRAM's, a 2Mx16b FLASH, and a coolrunner-II cpld; all sharing a common address/data bus. I'm interested in accomplishing the following:
- The ability to configure the spartan-3 from FLASH using the CPLD.
- Access to SRAM, FLASH, and a few memory mapped cpld registers using the Xilinx EDK/EMC core.
My confusion is with regards to how the address bus should be connected to the FLASH and SRAM's. The design's I have seen seem to connect the FLASH A0 to A1 or A2 of the FPGA address bus. Similarly the RAM is then connected to A2. My suspsion is that this is related to the data width of each device or the size of the data that is allowed to be written? I should note that my SRAM's are being used as a single
32b-wide memory and the FLASH and CPLD are only 16b wide. Anyway if someone could clarify the issue it would be much appreciated.Matt