I like their JTAG enable pin, so you don't have to loose valuable pins for JTAG - but they are narrow Vcc operation, and only promise < 100uA, and Xilinx do not have them on the on-line store, and are sparse elsewhere, so have that NFND look about them....
How long is your product lifetime ?
Yes, normally it is simply a SR latch, with some logic to catch S=R=H. When running, S,R cross their thresholds only briefly, to trigger the other phase.
-jg
Xilinx still sells much older CPLDs and the XPLA3 parts are 5 volt tolerant which may not be in high demand in new designs, but you can't easily design the part out with a non-5 volt tolerant part in its place.
I can buy them from stock at Digikey, so someone is still buying them.
Thanks for the tip. I think I will remember this circuit. It would appear to me that this circuit has more dependance on Vth and so would change frequency with temperature more than the three pin circuit which is supposed to be independant of Vth (of which I am not totally convinced). Peter's analysis of the three pin circuit looks pretty good. Any numbers available on the two pin circuit above?
Vth of CMOS does not change much with temperature, but the biggest variable, is the absolute value of Vth : that is a process variable. and being digital companies, FPGA vendors will not bother to band Vth as anything other than logic levels....
To check the dependance on Vth, simply drop any of these into spice :)
On the 3 pin one, as Vth varies one half of the cycle lengthens, whilst the other half shortens - so the frequency is nominally compensated, but duty cycle varies.
-jg
Your four pin scheme is a simpler solution if you have the pins, then you wouldn't need to find a small part with DLL/PLL.
Yes; I'd probably try a 2x clock with DDR I/O for the transmit waveform.
Sym>
Right, that clock modulation scheme duplicates the DC balance of the transmit data; 8B10B should be a nice fit, giving both DC balance and a sync mechanism for alignment.
Also, if you want to run near max cable/driver BW out & back, going to a 4x multiply at the "slave" instead of a 2x would make the narrowest modulated clock pulse width the same width as the bit period of the return data path, giving 1/4 rate outbound and 1x inbound data rates.
Brian
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