I have a design that will use a DDS synthesizer to generate an internal trigger rate for a pulse generator. The chip will be a ZYNQ
7020. The required upper frequency limit is maybe 20 MHz. The FPGA will have the usual, 48 bit or so, phase accumulator and sine lookup stuff clocked at maybe 100 MHz. The FPGA drives a fast DAC which in turn drives an LC lowpass filter and a comparator. Standard stuff.But could such a clock be generated entirely inside the FPGA?
Just using the MSB of the DDS phase accumulator works, but it will have one full clock, 10 ns p-p, of jitter. That will be ugly at 20 MHz. I've got to look into some sort of outboard analog filtering to clean up that single-bit clock, but I'm not optimistic. DDS is just too weird.
Do you suppose that one of the FPGA PLLs be used to clean up the DDS clock, scrub the jitter somehow? That could maybe be used over a modest range, octave maybe, followed by some dividers.
Any other ideas for making a programmable-frequency clock with DDS sort of resolution, but without all that outboard analog stuff?
I've been playing with sorta DDS in LT Spice, using a quantizer to approximate the DDS accumulator and DAC, but that's obviously not the best tool for this.