Electronic Dice ( 3 die ) In VHDL

How about using one LFSR per die pip? Using the SRL16s in Xilinx chips (don't know A, sorry), that would mean somewhere around 9 slices (for 3x6 pips), plus overhead, decoding logic, etc..., if I'm not mistaken? Incidentally, would using different polynomials effectively (as far as the human is concerned) decorrelate the LFSRs? Or would varying lengths (16, 32, etc...) do the trick? Or even, would different seeds be enough? I've never gotten around to studying the math, and never been great with statistics anyway... Pierre-Olivier -- to contact me directly, remove the obvious from my email --

in

Just because 16 sided dice aren't used doesn't mean they can't be done. I could supply three different types of 16 sided polyhedra, all with equal faces.

I was, after all, responsible for getting the 30 sided die on the market (back in the summer of '82).

Now it's FPGA design for me.

- John_H

There are two forms of an LFSR. One where the bits are just delayed versions and you have a huge adder that feeds the chain (good ol' Google says this is called the Fibonacci form). And there's another one where there are adders inbetween the registers so that the bits are not delayed versions of each other (called the Galois form).

Even in the case of the Fibonacci form, I have a feeling that grabbing a few adjacent bits will still produce a "random" number. Of course it depends on what you consider random, and I don't know much about the measurements they use for that.

Rejecting illegal combinations should be okay. The legal combinations will remain uniform. Unfortunately I don't know a good way to explain this. But you can take a six sided dice, reject values of 5 and 6, and have it act like a uniform four sided dice.

The only problem with the rejection method is you're not guaranteed a valid value every clock cycle, which is no big deal in this human operated push button application, but for some deterministic applications, you can't afford to wait for a "reroll" of the number.

--Vinh

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--Ray Andraka, P.E. President, the Andraka Consulting Group, Inc.

"They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759

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--Ray Andraka, P.E. President, the Andraka Consulting Group, Inc.

"They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759

Superb answer, Jonathan. I suspect that, even as you read this, someone is talking to their dean about transferring from electrical engineering to political science or animal husbandry.

And should you need it, I can give you the name of an excellent removing-tongue-from-cheek surgeon.

Take care, Bob Perlman Cambrian Design Works

I agree that you have to implement the full PRNG and not just use some bits of the LFSR, to get the full quality of the PRNG.

However, rejecting illegal values is IMHO a "good" thing to do, meaning that it doesn't bias. After all, each and every output value of the PRNG is "unpredictable" (within the quality limits of the PRNG). Thus, rejecting all 0x6 and 0x7 doesn't reveal more information than that the final output won't ever be 0x6 or 0x7. Still, an attacker can't predict any output value, given that he couldn't predict them already before we added the reject circuit.

It's a consequence of the lack of feedback into the PRNG. The PRNGs internal state is only changed through the intended means - by going from state n to n+1 (next value) etc. All cryptographic study that the PRNG design has received, inherently also applies to the combination of PRNG and rejection circuit.

The only disadvantage of this method is that the execution time is not predictable. Although highly unprobable, the PRNG could output 0x6 / 0x7 for a lot of cycles in sequence. Thus you don't know how long it takes to get an acceptable (legal) output. In this particular application (dice) however, I don't think that it will be a problem of significance.

Marc

arranged

Correct - and the design also does not have to have Mod 6 counting ->

Decoder; it is possible to count directly in either 7 segment Font patterns, or in Ray's Dice-Font pattern.

I have actually done a design that counts directly in 7 segment Font patterns (0..9) - the student can explain why that might be a good idea.

-jg

arranged

--

--Ray Andraka, P.E. President, the Andraka Consulting Group, Inc.

"They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759

--

--Ray Andraka, P.E. President, the Andraka Consulting Group, Inc.

"They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759

in the

Yeah adder isn't the best word, because the adders we normally think of have a carry chain. Modulo-2 addition has no carry, so it simplifies to an XOR.

Coming from Northern Ireland my 'irony detector' is stuck at

------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design

Then you've seen

could easily be done in a small CPLD and a short time with

With some care (challenge for todays students ?) I believe one can pack 2 dice into a 16V8 - smallest/cheapest programmable logic device made.

Ideal for backgammon etc....

What games need 3 dice ?

-jg

It was for a bar game, although there are several board games that use more than

Jim Granville wrote:

could easily be done in a small CPLD and a short time with

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--Ray Andraka, P.E. President, the Andraka Consulting Group, Inc.

"They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759