Efficient implementation of Address Decoding logic

First, your code (both versions) will create latches, not registers. You need a clock edge specification:

if rising_edge(clk) then

-- decode/assignment statements go here end if;

Second, whenever I see a long case or if-then-else tree, I look for ways to use an array, or array of arrays, to do the decoding for me, possibly within a loop. Think about transforming slices of the address into indices for the array, then assign the desired element(s) of the array from the data bus. For documentation, you can assign meaningfully-named constants to the appropriate index values, and use them where you want to individually access the contents by name.

Lastly, VHDL case statement targets are required to be mutually exclusive, therefore no priority is assigned. If-then-else statements do imply priority, but if the synthesis tool is smart enough to figure out that the conditions are all mutually exclusive, then it will remove the priority logic anyway.

if address = 1 then a

... if (and only if) two or more cases overlap.

Otherwise, excellent posting.

-- Mike Treseler

Mike,

You're correct, but the synthesizer must _recognize_ whether two or more cases overlap (i.e. if they are not mutually exclusive). If it cannot prove they are ME, then it must include (keep) the priority logic. In other words, priority is assumed for an if-then-else statement until proven otherwise.

Another way to imply priority (which the synthesizer can remove if it recognizes ME c>

Yes, of course, but if

*I* know that cases A, B cannot overlap, it is up to *me* to exclude special coverage of the (A and B) case in my description, if I want to save the gates.

I would say: ___________________ ... if A then do_A_thing; endif;

if B then do_B_thing; endif; ... ___________________ I see coding an if-then-else for this example as a logical error on *my* part, even though there is no functional difference.

-- Mike Treseler

Good point, but just for grins, let's turn this around into a read, rather than a write:

If a then data

I am using address decoding logic irrespective of the Clock i.e based on that particular address., i am implementing read and write functionalities.If i need a edge, could I use the /ARE low or /AWE low i.e if falling_edge(AWE)

-- decoding end if; Please clarify..

Since a and b are exclusive, I might save a gate by doing a single bit selection, if b_thing is ok as default data:

if a then data

If you use "falling_edge(awe)" then awe will get tied to the clock input on one or more registers that will hold the signal values that you assign within that if-then clause.

Storing data on falling edges of strobes will work, but think about what you are going to do with that data in the latches. The timing can be very difficult to manage if you need to use that data elsewhere in a synchronous (clocked) system. Handling asynchronous buses in a synchronous system is beyond the scope of this conversation. Whole chapters/books have been written on it. Generally speaking, you usually end up syncrhonizing the control lines, and using those synchronized versions to control storage into synchronous registers (i.e. they form clock enables on registers that are clocked by your system clock). If your clock is not fast enough to handle the timing of the controls, then you may need to latch the data with the asynchronous strobe, then use a synchronized version of the strobe to enable transfer from the latch into a register on the system clock.

Andy

Srikanth BJ wrote:

Andy., got to know many things from you. I havenot worked too much on handling asynchronous events., i think its probably very challenging and i guess one should be fully equipped with the basics involved. If you could suggest any book/links which might be very helpful to go further in to the above discussed topics, it would be really appreciated. Thanks in advance, Srikanth

Just google terms like "asynchronous" "synchronize" "metastable", etc. from this and the comp.lang.vhdl and comp.lang.verilog groups.

Andy

Srikanth BJ wrote: