I like to use a Xilinx written macro (edn) in my design using ISE 6.3. I seems ISE does not accept edn file. I could not find any documentation on using edn netlist for ISE. It follows the macro is little old and older foundation had provision where edn elements could be instantiated. However, I like to do this for ISE. The edn is synthesized and optimized netlist. Where in ISE design flow I can have this netlist recognized and interfaced with existing hdl or netlist files?
Thanks,