Hello, I am working with an unusual board that has two Xilinx Virtex 4 FX60's on it in a top/bottom mirrored configuration. (The BGA's are mounted above/below each other, with via's running between select pins to form mirrored pairs)
The problem I am running into is that both FPGA's must run identical firmware loads, and in some cases, this results in contention due to the mirrored pins. I do have a strap bit that can tell the design whether it is loaded in the top or bottom fpga, which I use to remap the inputs. (ie, in the top part, pin AG30 is used as the input, and in the bottom part, AG5 is used instead) These input muxes work fine using a similar concept.
The idea is that the fpga ID pin can be used to forcibly tri-state certain outputs in either the top or bottom design to prevent the contention. Since the fpga ID pin is an external input, the designs should be able to remain the same.
So, I created an EDK ip core in VHDL that instantiates an OBUFT, and connected it between the user logic and the external net. The VHDL is simply a wrapper. (I did implement a for/generate block to handle vectors)
The problem is that ISE is turning it into a LUT based AND gate instead, so I still get the contention. When I look at the pad in FPGA Editor, the T input is not mapped.
I'm using ISE/EDK 8.2.03i for this project.
Any ideas?
Thanks!