Dear
I would like to ask some help, for simulating EDK project.
I did following steps:
--------------------------------------------------------------------------------
- Generate "simulation model and compiler script" using EDK 8.2 tool.
- Compile design. " do system.do"
Following error ocurred:
----------------------- # ** Error: C:/Work/TEST/SimpleEDK8.2/pcores/mem_main/hdl/vhdl/ clock_dcm.vhd(19): Library virtex2 not found. # ** Error: C:/Work/TEST/SimpleEDK8.2/pcores/mem_main/hdl/vhdl/ clock_dcm.vhd(20): (vcom-1136) Unknown identifier "virtex2".
-----------------------
In the "clock_dcm.vhd", I commented following library definition:
-----------------------
-- synopsys translate_off
-- library virtex2;
-- use virtex2.all;
-- synopsys translate_on
-----------------------
Now "system.do" is compiled.
- Load design
"vsim system"
Following warning occurred:
----------------------- Warning: Component instance "ramx32 : ramb16_s36_s36" is not bound.
-----------------------
This means that BRAM block is present. I ignored this warning and proceeded to next step:
- Run simulation
Finally, following error occurred:
----------------------- # ** Fatal: (vsim-3421) Value 127 is out of range 0 to 5. # Time: 0 ns Iteration: 12 Process: /testbench/uut/buffer/out_mux File: C:/Work/TEST/SimpleEDK8.2/pcores/Buffer_Wrapper_v1_00_a/hdl/vhdl/ buffer.vhd # Fatal error in Process out_mux at
-----------------------
This looks like a logical error in VHDL. But this VHDL file is provided by the board vendor. I think I made mistake in the simulation process.
--------------------------------------------------------------------------------
My question is that
If I need to use following library "virtex2", how can I generate this library "virtex2"?
-----------------------
-- synopsys translate_off library virtex2; use virtex2.all;
-- synopsys translate_on
-----------------------
Thank you again.