Hi
while looking for help at Xilinx website I found already application notes about the DDR2 and Virtex5, but I am still having some trouble even with V4 DDR2 so I am looking for anyone who has succesfully used EDK DDR2 IP Core, it sounds and looks like easy to use, specially for the V4 the clocking requirements are relaxed, but well it doesnt work, well I am still fighting with it. To my big disappointment there are no example design available for EDK that use DDR2.
So I would be very thankful for any links points info an the use of DDR2 IP Cores with EDK for V4, yes I know the BEE2 project but those designs are all for DDR2 and V2Pro.
I might be able offer some reward for any actual help in this matter
Antti