EDK OPB DDR2 IP Core, looking for tested example

Hi

while looking for help at Xilinx website I found already application notes about the DDR2 and Virtex5, but I am still having some trouble even with V4 DDR2 so I am looking for anyone who has succesfully used EDK DDR2 IP Core, it sounds and looks like easy to use, specially for the V4 the clocking requirements are relaxed, but well it doesnt work, well I am still fighting with it. To my big disappointment there are no example design available for EDK that use DDR2.

So I would be very thankful for any links points info an the use of DDR2 IP Cores with EDK for V4, yes I know the BEE2 project but those designs are all for DDR2 and V2Pro.

I might be able offer some reward for any actual help in this matter

Antti

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Antti
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unfortunatly I managed to get the MCH_OPB_DDR2 ip core working myself :( there is no reward budget for me :(

so for anyone intererested the OPB_MCH_DDR2 IP core just works, there is one minor bug

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but there workaround is to implement the invisible in GUI wiring in MHS manually

Antti

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Antti

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