EDK/ISE : unroutable design

Hi,

I'm a Phd student using EDK (7.1i) in order to prototype a multiple processor system in a single chip.

I have made a design with 16 microblazes editing the ".mhs" file. Each processor can communicate with 4 other processors using point to point with DMA connections.

I used the fast implementation flow with default options in the "fast_runtime.opt" file.

The design seems to fit easily in a xc4vlx200 but I get the following output from the par tool:

Starting Router Phase 1: 273083 unrouted; REAL time: 42 mins 50 secs

[...]

IMPORTANT MSG: UNROUTABLE DESIGN; CHANGE PLACEMENT or EASE CONSTRAINTS Phase 4: 94054 unrouted;

[...]

34035 signals are not completely routed.

For more info about the design size Here is the output from map tool:

Design Summary:

Number of errors: 0 Number of warnings: 158 Logic Utilization: Total Number Slice Registers: 31,944 out of 126,336 25% Number used as Flip Flops: 29,896 Number used as Latches: 2,048 Number of 4 input LUTs: 48,510 out of 126,336 38% Logic Distribution: Number of occupied Slices: 36,209 out of 63,168 57% Number of Slices containing only related logic: 36,209 out of 36,209 100% Number of Slices containing unrelated logic: 0 out of 36,209 0% Total Number 4 input LUTs: 56,322 out of 126,336 44% Number used as logic: 48,510 Number used as a route-thru: 465 Number used for Dual Port RAMs: 4,096 (Two LUTs used per Dual Port RAM) Number used as 16x1 RAMs: 2,048 Number used as Shift registers: 1,203 Number of bonded IOBs: 4 out of 768 1% Number of BUFG/BUFGCTRLs: 1 out of 32 3% Number used as BUFGs: 1 Number used as BUFGCTRLs: 0 Number of FIFO16/RAMB16s: 128 out of 552 23% Number used as FIFO16s: 0 Number used as RAMB16s: 128 Number of DSP48s: 48 out of 192 25%

What are the possible ways to help the par tool find a sucessful placement/route?

Since I want to test a lot of different hardware configurations, I would prefer to implement my designs in a fully automated way.

Thanks for your help.

Regards, Lionel Damez.

Reply to
Lionel Damez
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Looks like the logic fits but the wires don't.

I wouldn't expect any latches.

placement/route?

Try a simpler case first. Maybe four microblazes?

-- Mike Treseler

Reply to
Mike Treseler

Try a simpler case first. Maybe four microblazes?

I have already tested simpler designs with less microblazes and place and route was successful with each of them.

What I want to know is how much processors can I put in a virtex4 device. I hope to put 32 in the largest devices.

Trying with 16 processors, I encountered this place and route problem.

The par tool outputs "CHANGE PLACEMENT or EASE CONSTRAINTS".

Is it possible to do that with the EDK interface, or do I have to export my design to Projet Navigator(ISE)?

Thanks, Lionel Damez

Reply to
Lionel Damez

The tool is telling you that 16 won't fit ... I doubt there is much you can do other than reduce the number of instances of the processor.

Mike

Reply to
Mike Lewis

- The logic for 16 microblazes fits.

- A single microblaze is routable.

- The communication between the prozessors is systolic.

From that information I would say that floorplanning is very likely to yield a routable design. This means that you tell the placer beforehand were in which reagion of the chip it should put each processor and the corresponding memory.

You can not do that from EDK AFAIK.

Kolja Sulimma

Reply to
Kolja Sulimma

Hi Lionel,

Sounds like you could use the new Xilinx PlanAhead floor planning tool:

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Since you are a doctoral student, contact the Xilinx University Program

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to see if they could donate it to you.

This looks to be exactly like the sort of application that Plan Ahead was developed for.

I would be interested in hearing about the results here on c.a.f. should you go that route.

Good Luck! Paul

Kolja Sulimma wrote:

Reply to
Paul Hartke

Mike Lewis wrote: >Lionel Damez wrote: > > Is it possible to do that with the EDK interface, or do I have to export > > my design to Projet Navigator(ISE)? > The tool is telling you that 16 won't fit ... I doubt there is much you can > do other than reduce the number of instances of the processor. > > Mike

- The logic for 16 microblazes fits. - A single microblaze is routable. - The communication between the prozessors is systolic.

From that information I would say that floorplanning is very likely to yield a routable design. This means that you tell the placer beforehand were in which reagion of the chip it should put each processor and the corresponding memory.

You can not do that from EDK AFAIK.

Kolja Sulimma

Thank you very much!

One other question :

The EDK tool generates a system with a flat hierarchy. If I add some constraints like closed area groups in the "system.ucf" in order to separate the processor subsystems, will that help for successful place and route?

Lionel Damez

Reply to
Lionel Damez

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