Hi,
I'm a Phd student using EDK (7.1i) in order to prototype a multiple processor system in a single chip.
I have made a design with 16 microblazes editing the ".mhs" file. Each processor can communicate with 4 other processors using point to point with DMA connections.
I used the fast implementation flow with default options in the "fast_runtime.opt" file.
The design seems to fit easily in a xc4vlx200 but I get the following output from the par tool:
Starting Router Phase 1: 273083 unrouted; REAL time: 42 mins 50 secs
[...]IMPORTANT MSG: UNROUTABLE DESIGN; CHANGE PLACEMENT or EASE CONSTRAINTS Phase 4: 94054 unrouted;
[...]34035 signals are not completely routed.
For more info about the design size Here is the output from map tool:
Design Summary:
Number of errors: 0 Number of warnings: 158 Logic Utilization: Total Number Slice Registers: 31,944 out of 126,336 25% Number used as Flip Flops: 29,896 Number used as Latches: 2,048 Number of 4 input LUTs: 48,510 out of 126,336 38% Logic Distribution: Number of occupied Slices: 36,209 out of 63,168 57% Number of Slices containing only related logic: 36,209 out of 36,209 100% Number of Slices containing unrelated logic: 0 out of 36,209 0% Total Number 4 input LUTs: 56,322 out of 126,336 44% Number used as logic: 48,510 Number used as a route-thru: 465 Number used for Dual Port RAMs: 4,096 (Two LUTs used per Dual Port RAM) Number used as 16x1 RAMs: 2,048 Number used as Shift registers: 1,203 Number of bonded IOBs: 4 out of 768 1% Number of BUFG/BUFGCTRLs: 1 out of 32 3% Number used as BUFGs: 1 Number used as BUFGCTRLs: 0 Number of FIFO16/RAMB16s: 128 out of 552 23% Number used as FIFO16s: 0 Number used as RAMB16s: 128 Number of DSP48s: 48 out of 192 25%
What are the possible ways to help the par tool find a sucessful placement/route?
Since I want to test a lot of different hardware configurations, I would prefer to implement my designs in a fully automated way.
Thanks for your help.
Regards, Lionel Damez.