edk clock problem

Dear all,

I am a graduate student at USF. I am working with XILINX XUPV2P board and i am using edk to interface memory and my RTL code (using import peripheral).

the RTL code synthesizes at 70 Mhz and EDK ddr memory access works in

100 Mhz.

However when i connect RTL to EDK using import peripheral, the design only passes implementation, place and route in 1 MHz, it fails to implement even in 25 Mhz.

my application requires ddr memory access and data transfer from edk to rtl and so on.

i really appreciate all ur suggestions. thanks for all ur help.

sincerely, Mahalingam

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mahalingamv
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