1. Home
  2. Field-Programmable Gate Arrays
  3. edk-chipscope 6.2 to 6.3 update

edk-chipscope 6.2 to 6.3 update

1) EDK 6.3 seems to have introduced a new SW bug, if the "global pointer optimization" is checked irratic behaviour happens. This is what caused problems to Rudolf Usselman (at least I think so)

2) Chipscope 6.3 HAS STORAGE Qualifier support, but only in ChipScope service pack!! and not for Spartan II-E, but only for newer families! well good thing of course in any case

Antti

Reply to
Antti Lukats
Loading thread data ...

Reply to
Symon

Please try SP2 when its out. This is fixed in the service pack.

Reply to
Vasanth Asokan

Yes! I agree 470%! (My approval percentages are arrived at with the same methods FPGA manufacturers use to come up with gate counts.)

Bob Perlman Cambrian Design Works

Reply to
Bob Perlman

Could you please open a case with our technical support hotline in regards to this issue and provide an example for the hotline engineer?

Matt

Reply to
Matthew Ouellette

Actually I think I use SP2 (EDK 6.3.1) and am still having the problem.

Best Regards, rudi ============================================================= Rudolf Usselmann, ASICS World Services,

formatting link
Your Partner for IP Cores, Design, Verification and Synthesis

Reply to
Rudolf Usselmann

impossible

ILA,

can

IT!

The storage qualifier is defenetly useful for some cases. But yes a more open OnChip Instrumentation would be nice. But It looks like none of the FPGA vendors is interested in it :( RE of ChipScope isnt so complex but it doesnt make much sense, it would better to design from ground up!

ChipScope ICON is actually a JTAG "Hub" that creates 15 virtual JTAG chains with 2 pairs of 16 update signals per port.

control[35:0] actually is TDI TDO TCK update_lo[15:0] update_hi[15:0]

update_lo[0] is used by all cores as enable for Serial ROM that includes the core ID and parameters. This serial ROM is scanned when Chipscope analyzer connects.

Altium Livedesign uses different approuch: for each core separate JTAG TAP instance is added, all those are added into secondary "soft" JTAG chain that is controlled over modified Xilinx Cable III where additional pins are allocated to the secondary soft chain.

Altera SignalTap is I think more similar to ChipScope where "hub" is added the FPGA intgernal TAP access primitive.

I do have some simple IP cores (in verilog) that can be connected to ICON and controlled by ChipScope analyzer, some JAM scripts that can work with ChipScope cores and some Windows application that also can trigger and read from ILA core.

please email me in private in case of interest.

Antti Lukats

Reply to
avrbasic

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.