EDK 8.2 Busmaster Example

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I'm just doing my first steps trying to get a busmaster
example created with xps running. There is some example code
and i just tried to use it for the first test. However it just
refuses to work and the busybit of the busmaster seems to stay
set. Has anybody an idea?


my c code:

int main (void) {
        Xuint64 *ptr;
        int i;
        volatile unsigned int a=1;
        unsigned char *control_register=(unsigned
        unsigned char *status_register=(unsigned
        unsigned int *ip2ip_addr=(unsigned
        unsigned int *ip2bus_addr=(unsigned
        unsigned int *transfer_length=(unsigned
        unsigned char *byte_enable=(unsigned
        unsigned char *go=(unsigned char*)XPAR_TEST_BUSMASTER_0_BASEADDR+0x10f;
        print("-- Entering main() --\r\n");
        while(*status_register & 0x40) ; //wait for busmaster to be ready
        *ip2ip_addr=(unsigned int*)XPAR_TEST_BUSMASTER_0_BASEADDR;
        print("busmaster transfer\r\n");
        for(i=0;i<1000;i++) while(*status_register & 0x40) ; //wait for
busmaster to be not busy anymore
        if(ptr->Lower==1) print("success");
        else print("failure");
        print("-- Exiting main() --\r\n");
        return 0;

This corresponds to the documentation in user_logic.vhd:
  -- Example code to demonstrate user logic master model functionality
  -- Note:
  -- The example code presented here is to show you one way of stimulating
  -- the IPIF IP master interface under user control. It is provided for
  -- demonstration purposes only and allows the user to exercise the IPIF
  -- IP master interface during test and evaluation of the template.
  -- This user logic master model contains a 16-byte flattened register and
  -- the user is required to initialize the value to desire and then write to
  -- the model's 'Go' port to initiate the user logic master operation.
  --    Control Register        (C_BASEADDR + OFFSET + 0x0):
  --       bit 0                - Rd            (Read Request Control)
  --       bit 1                - Wr            (Write Request Control)
  --       bit 2                - BL            (Bus Lock Control)
  --       bit 3                - Brst  (Burst Assertion Control)
  --       bit 4-7      - Spare (Spare Control Bits)
  --    Status Register (C_BASEADDR + OFFSET + 0x1):
  --       bit 0                - Done  (Transfer Done Status)
  --       bit 1                - Bsy           (User Logic Master is Busy)
  --       bit 2-7      - Spare (Spare Status Bits)
  --    IP2IP Register          (C_BASEADDR + OFFSET + 0x4):
  --       bit 0-31     - IP2IP Address (This 32-bit value is used to populate
  --                  IP2IP_Addr(0:31) address bus during a Read or Write user
  --                  logic master operation)
  --    IP2Bus Register (C_BASEADDR + OFFSET + 0x8):
  --       bit 0-31     - IP2Bus Address (This 32-bit value is used to populate
  --                  IP2Bus_Addr(0:31) address bus during a Read or Write user
  --                  logic master operation)
  --    Length Register (C_BASEADDR + OFFSET + 0xC):
  --       bit 0-15     - Transfer Length (This 16-bit value is used to specify
  --                  number of bytes (1 to 65,536) to transfer during user logic
  --                  master read or write operations)
  --    BE Register                     (C_BASEADDR + OFFSET + 0xE):
  --       bit 0-7      - IP2Bus master BE (This 8-bit value is used to populate
  --                  IP2Bus_MstBE byte enable bus during user logic master read
  --                  write operations, only used in single data beat operation)
  --    Go Register                     (C_BASEADDR + OFFSET + 0xF):
  --       bit 0-7      - Go Port (A write to this byte address initiates the
  --                  logic master transfer, data key value of 0x0A must be used)
  --    Note: OFFSET may be different depending on your address space
  --          by default it's either 0x0 or 0x100. Refer to IPIF address range
  --          for actual value.
  -- Here's an example procedure in your software application to initiate a
  -- write operation (single data beat) of this master model:
  --   1. write 0x40 to the control register
  --   2. write the source data address (local) to the ip2ip register
  --   3. write the destination address (remote) to the ip2bus register
  --      - note: this address will be put on the target bus address line
  --   4. write 0x0004 to the length register
  --   5. write valid byte lane value to the be register
  --      - note: this value must be aligned with ip2bus address
  --   6. write 0x0a to the go register, this will start the write operation

Re: EDK 8.2 Busmaster Example
Quoted text here. Click to load it
Ok, it is not the busy bit but the whole system is locked up. Nothing works
anymore after writing to the go register. Has anybody an idea, why?


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