EDK 8.1 SP1 released, DDR2 support is now included !!

Hi

EDK 8.1 SP1 was made available already on 17 Feb so a few days earlier then expected, and PLB DDR2 memory IP core is now really included.

some initial comments

1) the DDR2 IP core is different from MIG, so if MIG IP core required special loopback for the IDELAY calibration then the EDK DDR2 IP core requires DDR CLK feadback so there are different requirement for the PCB layout for DDR2 ip cores from MIG vs EDK

2) there DDR2 IP core documentation seems to be done in a rush, it still lists MCH_OPB (not PLB) in some cases and there is hint how to phase align of the CAL_CLK/4 should be, I would not like to use an extra DCM just to get 50MHz for the calibrate module, but I also dont know if is ok to use some not aligned clock for the CAL/4

3) the IDELAY_CTRL primitives seems to need handlocking constraints, at least on first attempts the design is unroutable :(

Antti