Editing bitstream

Hi all!

I am currently looking for an application note, a tech report or anything else that deals with Xilinx Spartan2 bitstream structure in order to edit bitstreams for this FPGA.

Someone has ever tried to do that ?

Cheers,

Grégory

Reply to
Grégory Mermoud
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Gregory, you have to be more specific about what you want to edit: BlockRAM content: easy LUTs: not too difficult Interconnect structure: forget it

Peter Alfke

Reply to
Peter Alfke

If you REALLY want to edit interconnect structure on a Xilinx FPGA, use one supported by JBits. But you really, REALLY don't want to.

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Nicholas C. Weaver.  to reply email to "nweaver" at the domain
icsi.berkeley.edu
Reply to
Nicholas Weaver

"Nicholas Weaver" schrieb im Newsbeitrag news:cruiv3$2n6e$ snipped-for-privacy@agate.berkeley.edu...

Is there a practical reason to do so?? Cant think of such a reason.

Regards Falk

Reply to
Falk Brunner

LUTs. But thanks, xapp151 came and told me the truth about it :)

But it does not seem to be "not too difficult" as you say. I need to make it completely automatic through a C program.

Maybe do you know any tutorial or further paper or application note concerning this problem ?

Reply to
Grégory Mermoud

A researcher working on routing algorithms.

A researcher looking to reroute designs to better handle partial configuration.

A researcher looking at how to deal with a large board of flawed FPGAs (a'la the old HP system), especially with easypath parts testing the LUT fully but not fully testing the interconnect.

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Nicholas C. Weaver.  to reply email to "nweaver" at the domain
icsi.berkeley.edu
Reply to
Nicholas Weaver

"Nicholas Weaver" schrieb im Newsbeitrag news:crv421$79c$ snipped-for-privacy@agate.berkeley.edu...

But this all is stuff done only by the Xilinx folks or people working close to Xilinx to improve the design flow tools (map/ p&R). And those guy for sure have much more detailed information (and tools) about FPGA connectivity. No normal mortal, ahhh user, does this kind of stuff, not even advanced users. But I wont stop anyone.

Regards Falk

Reply to
Falk Brunner

Uh, you'd be suprised what a researcher would want to do. EG, one research bit I did loaded Xilinx designs after placement but before routing, ripped up all the registers, duplicated them for C-slowing, retimed, reinserted all the new registers, and wrote back out the placement.

I could EASILY see an interesting research project which "meer mortal researchers" could attempt which would be take a bunch of easypath parts, map the actual defects, and route around defets albeit at a performance penalty.

It might be interesting to see if you colud use this to build a multi-teraflop vector supercomputer on a decent budget.

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Nicholas C. Weaver.  to reply email to "nweaver" at the domain
icsi.berkeley.edu
Reply to
Nicholas Weaver

mortal

Nick, as you know, there is no "bunch of EasyPath parts". By the nature of the beast, each and every one part is different. That makes your suggestion a formidably inefficient job...

Peter Alfke

Reply to
Peter Alfke

"Nicholas Weaver" schrieb im Newsbeitrag news:cs16o1$2619$ snipped-for-privacy@agate.berkeley.edu...

As I said, I wont stop anyone. But this looks like something for someone with too much free time on hands. No offence intended ;-)

Regards Falk

Reply to
Falk Brunner

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