Hi,
This may sound like an odd thing to want to do, but is there anyway to take an EDIF file, have it mapped and placed and then turn it back into an EDIF file? Specifically I want to be able to do this targeting a Virtex FPGA.
The reason I want to do this, is that I'm developing a design in JHDL, which seems to provide a nice interface for placing blocks of logic. For example, I can write 'place(blockA, RIGHT_OF, logicB)'. The catch seems to be, that for this to work blockA and blockB have to already have all their internal wires and logic placed. While technically I could do this manually, it is infeasible for the project I'm working on.
So I'm hoping there might be some way I can take advantage of another feature of JHDL, which is the ability to parse and translate EDIF into a JHDL representation. Then perhaps there is some way I can have the EDIF placed for me by external tools.
Is it the case that I'm simply asking for the impossible, wanting to place blocks logic relative to other logic blocks in a reasonably high-level and abstract way when targeting an FPGA?
Thanks, Jake