HI all how can one use an edif netlist of a design to add components to it either in schematic or vhdl and verilog? is it possible to do it in webpack? if yes then how? i have tried a lot and i can use command line tools to add ucf file and generate bit file from this edif netlist but i am unable to find a way to add further design components to it in schematic or vhdl design entry.
I can tell you how using VHDL. Please don't use schematics ;)
You will have a top level file in VHDL. Add a component declaration with the signal inputs/outputs of the edif file, and then instantiate it on your code and connect it up.
Create your project as a normal VHDL project that will be synthesized by XST. In the "Sources" window of ISE, the blocks that are using the edif files will show up as question marks. This is fine; XST will treat them as "black boxes". If you like to keep the edif files in a separate location, then on the "Translate" process, right click, select properties, and point the "Macro Search Path" to the location of your edif files.
Now just run the build. During the Translate phase, it should automatically find your edif files and include them in your project.
After using half a dozen different schematic packages over a period of about 20 years, I finally gave up on schematics about 6 years ago. I like schematics, but they simply are not portable, and you end up having to keep around an old computer and operating system and schematic software to support old projects. You really should abandon them; pick and use an HDL of some. I personally have never used the Xilinx schematic software, so I can give no help on that.
edif files are plain text, so they are easy to check. If your starting file is edif then look there. I have found that the top level entity name in the edif file needs to match the filename (or maybe I have not discovered the right flags to use). That is, if the file is xr16vx_1k.edf, then the top level entity within it needs to be named xr16vx_1k, and that is the name you instantiate within your HDL/schematic. It seems to me that when I have run into that error, it was not really the right location for the error. Check all the signal names and the top level edif entity name.
In the edif files I have used, above the "design ROOT" section (which does indicate the top level), there should be a "cell ROOT" section, and within that an "interface" section which will list the ports.
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