Hi
I am using synplify to synth a design with some xilinx core gen devices. get warnings on some of the core gen edif files stating that there is a interface mismatch between the verilog and the edif. I can only assum that it is something that core gen is not doing correctly. Has anyone els seen this problem? Here is the warning I get.
@W: : | Interface mismatch for Entity/Module dplbuf_16x512
Give us the Coregen version, OS, object and parameters so we can reproduce the problem.
Synplify can handle these details for you if code your buffer from their synthesis templates instead of using coregen netlists directly.
-- Mike Treseler
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