dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs

In article , Nick Camilleri writes: |> If you know of a killer-app for partial reconfiguration, I'm sure we |> would be happy to listen and try to meet the market's needs.

See, and that is the problem.

As of now, research is actively pursuing what could become the next set of killer apps. Just check out for the vast efforts being currently put into "reconfigurable computing", "organic computing", "adaptive computing" to give a few buzzwords.

Xilinx seemed to have *the* ultimate product for that, but despite all claims, PR support is hardly there. There have been some few successes in this field (e.g. Becker et al. from Univ. Karlsruhe), despite all hassles with varying ISE versions. But in the end, there are still too many obstacles to really *use* PR.

Forgot the name, but in this very thread some other poster described his experiences and how they basically came down to getting to know which (sub)version of ISE supported what, and which versions were broken with respect to PR. Which is exactly our experience as well.

A couple of weeks ago David Kramer posted in this group for specific help regarding problems with PR [1].

I didn't see one single answer from "you Xilinx guys" *here* regarding his topic.

After all, fpga_toys has a point: You are advertising a feature which basically is broken. In hardware it's supported, but using your development software it's rather inaccessible without jumping through a good number of hoops. Personally, I'd be more than lucky if there would be an easy way to accomplish the following:

- creating an internal bus connecting a number of same-sized "slots", i.e. regions within the FPGA to be filled with exchangeable functionality

- being able to exchange the functionality of those slots on the fly (dynamical partial reconfiguration)

- do that with Virtex-IIpro and Virtex-4FX

I don't mind if that works only through a shell script (in fact, I'd prefer it that way), if it works at all without throwing INTERNAL_ERRORs and FATAL_ERRORs -- and if it works consistently and not with one specific subversion of one specific ISE version so that when I upgrade the software the design isn't broken or having to chose which chip family I can't use for being able to do PR.

Don't ge me wrong: as a university researcher I am more than thankful for the support Xilinx gives us. But as of now I have a feeling that PR on Virtex-II/4 might vanish like XC6200 did vanish end of the 90s just because of the lack of proper software support: if a hardware feature is not properly accessible via the development software it won't be used. Therefore no multi-million dollar revenue will come from that, and following your argumentation you won't put major effort into it if you can't be sure that there's a multi-million dollar revenue to expect.

That's a vicious circle only *you* can break: either by releasing software which supports PR without major obstacles, or put out enough information (could be under NDA, as I'm not that religious to demand that everything is open-sourced) so that fpga_toys (or whoever) is able to build supporting software.

Rainer

I'm not that religious about open source either. But I also see that some perception of value needs to justify the cost in corporate america, or the board will question wasting the dollars that the stock holders have a right to expect be spent for value.

I don't see another solution at this time.

I do know that RC on xilinx is dead with the ISE tax to use such a computer or accel card, and for a product that doesn't even support RC as it needs to be supported in a high value multiprocessing multiprocessor FPGA based computer.

Clearly Xilinx thinks this will not be a high volume revenue source, and compared to dedicated sales they are probably right. So we can never expect support at the levels needed to support good RC and PR on their product line. It's not right to bitch at them for not doing a better job when the revenues aren't likely to cover the work.

I do think that asking them to open up enough we can support ourselves is of value, and they have the right to decline. At least everyone will know the rules of the game, and not waste their energies on a dead end Xilinx RC and PR dream if they refuse. There are other vendors that might see this as their gold mine, and openly support developers helping them.

I've read Neal Steiners thesis and related papers several time over the last couple years (etd-09112002-143335):

A Standalone Wire Database for Routing and Tracing in Xilinx Virtex, Virtex-E, and Virtex-II FPGAs

Along with the papers for VPR and VPR for Virtex, JHDL docs, and several related projects.

That however, doesn't describe the work necessary to do a good router for Virtex-2, Pro, or Virtex-4 products .... which I believe is info only available from Xilinx.

Any other suggestions for doing our homework?

Frame based partial reconfiguration is really neat. Next time I will definitely try them out, but is the software available in Webpack 8?

I am responsible for the partial reconfiguration software. Let me try to answer all of the questions posted:

Q: Does the released ISE software support partial reconfiguration? A: In some cases, yes.

Q: Does anyone have a commercial product that successfully employed partial reconfig? A: Yes, there are a few.

Q: Why did Xilinx say partial reconfig worked when most of the time, it doesn't? A: We released software for partial reconfig about 4 years ago. At that time, there was a flow that worked if you did everything in the right way. There were a couple of people in my group that were assigned to help customers through the mine field. It was rare that our sales force told us about customers using partial reconfig, so we assumed that nobody was using it. Because of other priorities, and the apparent lack of interest, the partial reconfig software languished.

Q: Is there a killer app that will drive Xilinx to put the effort needed to make partial reconfig a workable flow? A: Yes. There are software defined radio applications that are lucrative enough to get our attention.

Q: Does Xilinx now have software that works for partial reconfig? A: Yes. We have a team that has modified the current software, created a new flow, and tested the software with different applications. In addition, PlanAhead makes it much easier to lay out your design and run DRCs to ensure that partial reconfig will work.

Q: How do I get this software? A: Contact your local FAE. If you're at a university, contact the university program. Our Xilinx Labs research department is supporting the universities.

Q: Why don't you release the software with ISE? A: The plan is to release it with ISE in version 9.1i. For now, we have an efficient team assigned to refine the flows and fix bugs as soon as they are found.

Q: Is frame reconfiguration really cool? A: Yes. However, Virtex2 and Virtex2-Pro together with our new software let you do what could be considered a partial frame write. Even though you are writing the entire frame (column), Virtex devices don't glitch when you write exactly the same config bits. This allows you to have static logic above or below a reconfig region. We reconfigure the static region, but it continues to work. This also allows us to have static routes that pass through a reconfig region. The software reserves these routes when routing the reconfig region.

Q: The software license fees are $3k - $5k. How can we use this for reconfigurable computing? A; I'm not sure where these prices came from. If you are creating a reconfigurable computer, contact me and we can discuss an OEM deal for much less money.

Q: Should I feel comfortable adding partial reconfig to my current application? A: Personally, I would wait a couple of months. We are currently rolling out the software to our SDR customers and will be spending our effort supporting them. In addition, many of the FAEs have not been trained on the new partial reconfig flow. And they are the first line of support.

Steve

Hi Sean,

Your diploma thesis looked for the same goal than my PhD. Thesis. I was working with MicroBlaze in Spartan-3 (there is not ICAP, but it is possible the self-reconfiguration too). I know another student working with OpenRISC is Virtex-II. PR works reasonably well in these two systems. I succeed in obtaining PR coprocessors.

Regards,

Ivan

Hi Steve,

thanks for your answers.

Yes... I am working on it ;)

Regards,

Ivan

That's nice, I guess I will give our discontinued SDR project another chance. What is the estimated time of ISE 9.1i release?

thanks everyone to give those advices , I try to use the ISE 8.1 to do PR with the methode difference-based partial reconfiguration , =E7a marche , but I never find out the differents with the others version. and someone said the PlanAhead provides a single envirenement to manage the preceding guideline but it must call my local FAE, so I dont know how easy with it for the PR . if anyone knew it please told me! thanks a lot regards

xun

January 2007

I am working on it also , O_O

xun

Hi I am a student, write a diploma about application of partial reconfiguration. Would not you to give me materials where is the fast-acting with partial reconfiguration and without it compared? Beforehand thankful.

John Williams' "Partial Reconfiguration on Xilinx Devices" email list is another resource:

The archive is available here: