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DVI-decoder clock question

Let say I have two DVI streams - generated by two encoders, those have different video contents but same pixel clock

The two tmds streams travel thru cables then - are decoded by two decoders - then fed into an FPGA

The question is how the two clocks at the output of the encoders look like, are they the same? Can we use only one clock for both channel to clock the data in the FPGA?

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My theory is that, the original clock goes to two 10x then divided back 1/10, so they are supposedly be in same phase... or what else ???

Reply to
Mawa_fugo
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Although you may make it work in the lab, I doubt that you can robustly use only one clock. If the encoders are using different crystals, their frequencies will be slightly off and will drift over time. This will break things. Also, each of the encoders may change their phase relationships as they warm up.

If you're running at high clock rates, you're headed for a lot of heart-burn.

John P

Reply to
johnp

If the same source is used for the pixel clock of both encoders, and by same I mean only one physical clock oscillator is used for both encoders, then you can be sure that that the bit rate for both encoders is the same. However, there will be no guaranteed phase relationship between the data output of the two encoders.

You could use the same original clock source, or one of the two clock outputs from the encoders, and a dynamic phase aligner for the receivers in the FPGA to cut down on the clocking resource requirement in the FPGA. However, you may find it easier to use the clock/data from each encoder to capture the data and then put it through a simple shallow depth synchronous FIFO and use a single global clock for the rest of your system.

Ed McGettigan

-- Xilinx Inc.

Reply to
Ed McGettigan

Good idea, that's what I'm heading to - thanks all for advices

Reply to
Mawa_fugo

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