Duty cycle constraints and internal pulse shaping

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In Xilinx ISE/Webpack, among the clock constraints you can also define
the clock duty cycle. Why? I believed that all flip-flops were
edge-sensitive. Is the placer&router somehow influenced by these
constraints? If yes, how?

My question comes from a practical problem I'm having. I need to use a
short pulse (around 4-5 ns) as a clock in a Spartan2 (the frequency is
around 100 MHz, but the problem persists at frequencies a lot lower).
Apparently, even if the FF should be edge-sensitive, there are a lot of
problems with short pulses, sometimes the edges are ignored or
"doubled". My first idea was to "enlarge" the pulses by using a FDC with
CLK connected to pulse, D connected to VCC and Q connected to CLR
through some "delay" logic (buffers, inverters and so on), in order to
have some propagation delay added to the pulse width. This solution
worked poorly: sometimes I compile the project and the FPGA works
nicely, but if I just add a flip-flop or move a signal and recompile the
project, the result is totally unknown. Since I need to change the
firmware often, and I can't test it every single time, this is bad.

Now I have found a way that seems to work always, the schematic is like


But I don't think it's very orthodox. :) So I remembered the duty cycle
constraint. Could it help? Actually I need an input stage able to accept
either negative and positive pulses, so the duty cycle would vary from
nearly 0% to nearly 100%.

(of course: no, I can't add external circuits)


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