Hello,
Is there someone who has experiences with designing a dual port RAM. I use the device Spartan-IIE (XC2S300E). But it should be simular with other devices (e.g. Virtex, Spartan 3, etc) I know there is a Synthesis Template in "Xilinx ISE Foundation". Is there someone who knows about a complete design for a dual port RAM. I know, I need to get some more experience with VHDL.
Thank you for any help.
Tobias Möglich
I used that template without problems. But I assume that you can't use single-bit signals as RAM-data-inputs.
some Code:
multibit
Try Core Generator "Tobias Möglich" ?ÈëÏû?ÐÂÎÅ : snipped-for-privacy@gmx.net...
Tobias,
Have you tried using the Xilinx Coregenerator to instantiate the Dual port BRAM ?
-pradeep
Tobias Möglich wrote:
It is possible to use single bit signals al long as you define them as a std_logic_vector (0 downto 0). This vector can be converted to a single signal by the statement signal Hello Tobias,
Hello!
Thank you for your advice. Yes, I tried it the CoreGenerator. Hm. One more question: Do I have to copy the source code generated by the CoreGenerator in a vhd-file or is it enough to add the generated core (-> including the xco-file by saying: "New Source... IP(CoreGen & Architecture Wizard) in Xilinx ISE Foundation)?
Tobias
>"Tobias Möglich" schreef in bericht news: snipped-for-privacy@gmx.net...
saying:
Foundation)?
The source code generated by the core generator is only needed for simulation. You can just add the generated core to your project and create an instance in the right HDL file or schematic
Mark
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