Hi all,
My ASIC design requires dual port memories(one port R/W other port only read) but there is a constraint on using it. Instead I am planning to create this memory using single port RAM's.
Writes to this memory take place at 60 Mhz while reads can occur at freq varying from 5-30 Mhz.
Is there some way out?
If you can allow waits on either port then you should be able to do this. You would need an arbitrator that can detect when the memory is in use from one port and hold off the other port until the pending transaction is finished. You'll need to be careful in your arbitrator design to make sure you don't have problems with requests coming in at the same time, and with your system design to make sure that the waits are OK.
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You an use two RAMs if you have enough RAM availabe in your ASIC. Simply write into both RAMs using the same address and data.
Petter
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At the very low write and read rates that you mention, just run the memory at 120 MHz cycles, and use every even numbered period to write, and the odd one to (potentially) read. This may need a little finesse if your reads are asynchronous, but would otherwise be simple and economical. Peter Alfke
Hi Petter,
I was trying to do the same, using 2 SPRAM's & writing to both of them simultaneouly using same address & data.
addr_0 = ~pa_rwb ? pa_wraddr : pa_rdaddr; (port A is R/W port)
addr_1 = ~pa_rwb ? pa_wraddr : (pb_rwb ? pb_rdaddr : 8'b0); (port B is read only port)
In a dual-ported RAM, you have two independent access mechanism to the common data, so you can read while you are writing. (In a "true dual- ported RAM" you can also have two independent write, or two independent read opertions going on simultaneously) But you still have to avoid simultaneous read and write to the same location. (Contention) You avoid (almost) all these problem with Time-Division Multiplexing, as I mentioned in my previous post. Given your extremely slow speed, that's the way to go! Peter Alfke
Hi peter,
If I understand correctly, you are say> In a dual-ported RAM, you have two independent access mechanism to the
Hi Peter,
Another thing, what if I dont have the double clock available in the design?
Thanks > Hi peter,
My suggestion is you design for the worst case..... if u duplicate the rams u will automatically get multiport reads.... you can create any multiples of frequencies from the DCM....
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