The setup: Virtex ( >= 2 ) Dual-port BlockRAM configured with both ports in "Write first" mode. Both ports have the same (global) clock and the same address, with Enable tied high, so they are both always reading.
Part 1: Cycle 0- (init value) WE to port A, with DI = 0. Cycle 1- (change value) WE to port A, with DI = 1. Cycle 2- (cycle 1 results) Output A is 1 because it is in write first mode and 1 was written in cycle 1. What is value at output B during cycle 2? a) 0 because port B is not being written to, and reflects the value it would have read if there was no activity on port A. b) 1 because port A is in write first mode, and the activity on port A interferes with port B. c) x Don't do this, the result is indeterminate.
Part 2: same as part 1, with A and B switched Cycle 0- (init value) WE to port B, with DI = 0. Cycle 1- (change value) WE to port B, with DI = 1. Cycle 2- Value at output B is 1 because it is in write first mode and 1 was written in cycle 1. What is the value at output A during cycle 2? a) 0 ... b) 1 ... c) x ... I said don't do this!!!
I'm hoping the answer to both Part 1 and Part 2 is a), because it simplifies a 2-D 5x5 Gaussian filter I'm putting together (eliminates muxes and registers external to the RAM, and this is going into an already very tight design).
Peter tells me c) for both (I think).
Meanwhile, XST user guide gives DPRAM inferring VHDL which sims a result of b) for Part 1, and a result of a) for Part 2.
My first instinct is to trust Peter, but the fact that the XST user guide gives deterministic code gives me pause.
So I put it to the group, hoping someone has actually used this setup and has some definite answer. I'm a day away from coding up a test circuit to find out what the silicon really does, but if anyone knows of anyplace where operation in this scenario might be documented, it would save me a few hours. Thanks all, Just John