Hi there,
I am working on a high-speed (500 MHz, Virtex 4, speedgrade -12) and multi-precision adder (unsigned) capable to compute 256 bit additions using the DSP48 slices. I am using a sequential adder design, thus passing a chunk with the lowest bits to a DSP adder slice fist (each chunk is only 32 bit for internal reasons), continuing up to the highest bits of the input computing a 32 bit result each clock. When implementing the carry logic between the chunks, I just came across with its funny realization in the DSP slice. You can either use the fabric to determine the carry yourself (1) or use the inverted MSB from the output P[47]/PCIN[47] (2). Using the fabric (1) for carry implementation requires the additional CARRY_IN register to preserve the maximum clocking speed of 500MHz making it necessary to wait for the carry until the computation of the next chunk can start. Option (2) seems not to be applicable to my problem due to the inverted carry signal which is useless for my scenario. Does anybody have a good solution to this?
Thanks already in advance! Cheers, Tim