DSP48 carry logic for multi-precision addition

Hi there,

I am working on a high-speed (500 MHz, Virtex 4, speedgrade -12) and multi-precision adder (unsigned) capable to compute 256 bit additions using the DSP48 slices. I am using a sequential adder design, thus passing a chunk with the lowest bits to a DSP adder slice fist (each chunk is only 32 bit for internal reasons), continuing up to the highest bits of the input computing a 32 bit result each clock. When implementing the carry logic between the chunks, I just came across with its funny realization in the DSP slice. You can either use the fabric to determine the carry yourself (1) or use the inverted MSB from the output P[47]/PCIN[47] (2). Using the fabric (1) for carry implementation requires the additional CARRY_IN register to preserve the maximum clocking speed of 500MHz making it necessary to wait for the carry until the computation of the next chunk can start. Option (2) seems not to be applicable to my problem due to the inverted carry signal which is useless for my scenario. Does anybody have a good solution to this?

Thanks already in advance! Cheers, Tim

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Tim
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Reply to
Peter Alfke

Thanks for your response, Peter! My favorite carry handling would be a solution with which I don't need to leave the dedicated silicon to save on additional register (and latency) stages which would be necessary to keep the high frequency constraint (500MHz). Additional latency would delay the next computation of a 32bit chunk significantly demanding for a much higher cycle count for the entire 256bit addition. Do you have a good idea how I can pass on the 33rd carry bit (or upper bit if sign extended) between the computations and DSP slices without using the fabric? It would be so easy, if the P[47]/PCIN[47] carry logic wouldn't be inverted...but an inverted carry is probably quite useless for my desire.

BTW: what is the reason for the inverted P[47] carry logic?

Thanks again ;-) Tim

Peter Alfke schrieb:

Reply to
Tim

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