DSP

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Hi, <BR>
I am working on a project of a dc-dc converter wherein we require to  <BR>
generate hardware implementations from z-transform equations.  <BR>
My fellow researchers are using system generator and simulink to  <BR>
generate hardware implementation from the z-transform equations on  <BR>
FPGAs.(that is they get differential equation in terms of z^-1, z^-2 etc. for
e.g. they realize 1.8*z^-2 using a constant element, a multiplier and two Z^-1
delay elements) <p>However, I need to implement those z-transform equations on
CPLDs.  <BR>
I wonder if i could use system generator for that. <BR>
but nowhere in xilinx website or system generator documentation is  <BR>
there any mention of CPLDs. everywhere it says that DSP  <BR>
implementation can be done by system generator on FPGAs. <p>however one thing
that intrigues me is that if all system generator  <BR>
does is to generate vhdl code for the hardware implementation from  <BR>
the z-transform equation(xilinx blocks) then why can't we use that  <BR>
vhdl code and generate the same hardware on cpld. <p>if someonce could throw any
light on this issue i'd be highly obliged. <BR>
or if you know someone who you think might be able to guide me on  <BR>
this please pass me his email address.  <p>sincere regards, <BR>
vishal shah

Re: DSP


I think you'd probably be better off just writing the HDL directly from =
your Z-transforms. It would be faster and you'd have more control.  But =
that's a different matter.

If you look at the HDL you can tell it it will port to CPLDs.  If it is =
just RTL source, it should port fine.  Most likely, though, it will =
instantiate a lot of primitives that aren't available on a CPLD, which =
may be another reason to write the source directly.  I can't imagine =
that SystemGenerator code is highly portable, or it would be portable to =
a competitor's part.

The main problem you are going to have, though, is that the CPLD just =
won't have enough gates to do what you want.  The Virtex-II parts have =
embedded multipliers for DSP operations, and the other families have =
families have hardware to make implementing multipliers easier.  =
Multipliers may not be feasible on a CPLD.  You might only have room for =
the smallest of operations.

-Kevin
  Hi,20%
  I am working on a project of a dc-dc converter wherein we require to20%
  generate hardware implementations from z-transform equations.20%
  My fellow researchers are using system generator and simulink to20%
  generate hardware implementation from the z-transform equations on20%
  FPGAs.(that is they get differential equation in terms of z^-1, z^-2 =
etc. for e.g. they realize 1.8*z^-2 using a constant element, a =
multiplier and two Z^-1 delay elements)20%
  However, I need to implement those z-transform equations on CPLDs.20%
  I wonder if i could use system generator for that.20%
  but nowhere in xilinx website or system generator documentation is20%
  there any mention of CPLDs. everywhere it says that DSP20%
  implementation can be done by system generator on FPGAs.20%

  however one thing that intrigues me is that if all system generator20%
  does is to generate vhdl code for the hardware implementation from20%
  the z-transform equation(xilinx blocks) then why can't we use that20%
  vhdl code and generate the same hardware on cpld.20%

  if someonce could throw any light on this issue i'd be highly obliged. =

  or if you know someone who you think might be able to guide me on20%
  this please pass me his email address.20%

  sincere regards,20%
  vishal shah


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