Hi everyone, I am using a demo board from Memec whose clock source is given to one of the input PINS of the FPGA. I have to generate two clocks of different frequency from this input clock source. I am using two DCM's for these. When i give the input clock to both the DCMs there is an error during implementing the design which says one input clock cannot drive two DCM's or something like that. So i tried giving the output of one of the DCM's to the input of another DCM. Even then it gives an error during the implementation stage. Both the error cases are mentioned below.
This problem has been addressed before in this group without any possible solution. But it has been a long time. So i was thinking anyone has come up with an idea. I have also opened a webcase with Xilinx. The first case is when the input clock is given as an input to both the DCM's The second case is when the output clock of the DCM is given as an input to the second DCM.
case1 ERROR:LIT - IPAD symbol "clkin" is driving more than one loads. IPAD can only drive a single IBUF or two IBUFDS. If you are using a BUF instead of an IBUF, it may have been simplified, please use an explicit IBUF instead. Errors found during logical drc.
case2
ERROR:NgdBuild:455 - logical net 'CLK0_OUT' has multiple drivers. The possible drivers causing this are: pin O on block dcm_33_CLK0_BUFG_INST with type BUFG, pin PAD on block CLK0_OUT with type PAD ERROR:NgdBuild:466 - input pad net 'CLK0_OUT' has illegal connection. Possible pins causing this are: pin O on block dcm_33_CLK0_BUFG_INST with type BUFG Thanks and regards