Downloading external data file to FPGA

Have a look at the .coe file in google. You can instantiate your rams by this file through core generator (this is for xilinx). Or you can define your own ram so that you can instantiate your ram as instantiating an array. Have a look at Mike Treseler's home page. Chipscope only makes you see what is going on FPGA.

--enes

Thanks Enes, but the problem is that I still have to resythesize the whole design if I use the Core generator. XST allows allows to specify the RAM data in a text file and I can read then the contend from this file when running the architecture. However, I havent found any option in Chipscope nor Impact that allows me to download such a data file to the FPGA. SO I wonder if the only way to do that is using an UART Interface?

Cheers, F.

e?

Hi Florian,

Actually I haven't been in such a situation before but as I know this is not possible by using these tools. You have to reach to the rams externally via a protocol. If there is something like you said, which I don't know, I will be glad if I can learn it too.

Regards

--enes

I'm not aware of any tools that would let you change the contents of RAM in a configured FPGA without requiring you to design your own interface and logic to write received data into the Block RAM. I've often thought this would be a useful feature (It would be especially nice to be able to dump the contents of a block RAM with Chipscope).

What is possible is to change the data in the configuration bit stream so that when you configure the FPGA the RAM is initialised with the data you require, without having to iterate through synthesis and PAR. It's been a while since I did anything like this but I seem to remember there is a tool included in the Picoblaze package from Xilinx called Data2Mem that did exactly this to include the code for the processor in the bit stream. Take a look at the flow this tool required and you should be able to adapt it to your needs.

Simon

Hi, I think that Chipscope allows text file to be applied at input of certian module through VIO core. A slightest of logic across VIO can allow initalization of BRAMs at run time.

I never tried this, just an idea

/MH

Hi, I think that Chipscope allows text file to be applied at input of certian module through VIO core. A slightest of logic across VIO can allow initalization of BRAMs at run time.

I never tried this, just an idea

/MH

Hi, I think that Chipscope allows text file to be applied at input of certian module through VIO core. A slightest of logic across VIO can allow initalization of BRAMs at run time.

I never tried this, just an idea

/MH

Sorry for Multiple post..Must be some fault with my browser

Hello Florian,

I have had exactly the same trouble as you did and I never found a solution either. UART is too slow for this purpose at 10kB/second.

I think ideally I would like to use ethernet interface for data communication. I've looked into the opencores IP cores and some of the MAC cores can be useful.

The problem with using ethernet interface is then I also need to design a custom RAM interface to interact with the ethernet interface. This quickly grows beyond my time and capability as a fpga hobbist.

My board (spartan 3A) has all the features to set up something like this to happen. If you want to go this direction for data communication, I can work together with you.

Fei

If the data is fixed, it is easy to declare a vector array in vhdl to infer a block rom. No write interface required.

-- Mike Treseler

snipped-for-privacy@googlemail.com wrote: (snip)

Xylinx used to publish the information on where the LUT bits were stored in the configuration file, for the case of LUT based RAMs. (Among other reasons, so that comparisons with read-back data could be made.) Without that, you can compile different RAM initialization data and compare the bit streams.

-- glen