When I simulate my System Generator design, the following error is reported: "Although the behavior of this block, as configured, could be simulated, it will not be possible to target it to hardware because: --- Cannot be synthesized and it does not map to cores because the FFT core must be run at the system clock rate" The problem apears when I put a Down Sample block before the FFT inputs, to obtain a zoom effect in simulation. Anybody can help me?
- posted
20 years ago