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Doubts on IBUFGDP

Hi all, I am doing a DDR SDRAM design which is obtained using the MIG tool. The target device is V4LX60. But in that i observed a problem that the controller is using differntial clocking. And IBUFGDP is used to buffer the clcok. The problem is controller needs two differential clcok signals. But the demo board support only one. Tried to assign the same clock to different IBUFGDP units but in the par state it showed an error. Is it possible to assign a differntial clcok signals to two different buffers. Second question is what is the risk involved in changing the RAM controlller code to work with single ended clock. I am planning to use

160 MHz for RAM operation. regards Sumesh V S
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vssumesh
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One clock runs the IDELAY and the other clock runs the MIG logic. Thanks to a timely answer in comp.arch.fpga

we know that the IDELAY can run from 180MHz to 220MHz and can be driven from a DCM (thanks, Peter!). You can go through the MIG code and find where the reference clock has its IBUFGDP, delete the IBUFGDP, take the clock signal and connect it to any clock you have lying around that meets the 180MHz to 220MHz spec (or use a DCM output to generate one).

Shouldn't be a problem using single-ended, but if you can increase the rate to 180MHz, you can use the same clock for the IDELAY.

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Joe Samson
Pixel Velocity
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Joseph Samson

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