doubt in verilog coding

hai, i am vishnu i have some doubt regarding verilog coding,i want to have 5 secs delay ,as delays are not synthesziable i have used counter, but my problem is i want to use that counter inside an always block,i have tried using events but that too are not synthesizable,i hope u can solve my problem

Reply to
ravipativishnu
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That's the way to do it.

You already solved it...use a counter. If putting the counter indisde an 'always block' causes you grief then don't do it

Kevin Jennings

Reply to
KJ

In my case the clk frequency is 4.4MHZ, I need to have 5secs,10secs and 25secs delay,from my calculation the required is 20 bit counter,I have written the code below

module delay(osc,count);

input osc; output [19:0]count; reg [19:0]count; reg inter;

always @(posedge osc) begin count

Reply to
ravipativishnu

Reply to
Rob Dimond

thanks rob I will try coding my project using state machines ,still i have one doubt I am using QUARTUS-2 software in this events are not synthesizable so how to take care of events in that.

regards vishnu

Reply to
ravipativishnu

Reply to
cs_posting

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