Hi folks,
Been checking the archives for an answer to this one without much luck...
What does doubling the clock rate of a design on an FPGA do to the power consumption (in general - I am just looking for a rule of thumb here..)?
If you need some assumptions to answer:
Assume: critical path is a 25-bit carry chain in an adder. a highly pipelined design occupying most of the device.
Not sure what else would be useful assumptions-wise - please feel free to add your own! :-)
Also, if I double my clock rate and reduce my hardware by half due to sharing hardware over 2 clock cycles, obviously the reduced hardware will reduce power consumotion and the increased clock will increase power consumption, question is, which is the overriding factor? (the clock I guess?).
Again, just looking for a rule of thumb.
Cheers,
Ken