Does anyone know how can I get started on making a DOS script file to synthesize a VHDL design. I tried understanding something from:
But I still need more help. Can someone please tell me the sequence which I should follow.
Thanks
Does anyone know how can I get started on making a DOS script file to synthesize a VHDL design. I tried understanding something from:
But I still need more help. Can someone please tell me the sequence which I should follow.
Thanks
This is how Mentor's HDL Designer does it (auto generated)
syn.bat:
"C:/Xilinx/bin/nt/xst.exe" -intstyle xflow -ifn cpu86.xst -ofn cpu86.syr
cpu86.syr: output log file
cpu86.xst: contains the project as shown below (note not all synthesis settings shown):
set -xsthdpdir ./xst run
-ifn cpu86.prj
-ofn cpu86
-top cpu86
-p xc3s500e-cp132-4
-uc cpu86.xcf
cpu86.prj: contains the file list
vhdl cpu86 proc_rtl.vhd vhdl cpu86 cpu86_struct.vhd
cpu86.xcf: contains the UCF settings:
NET "clk" TNM_NET = "clk"; TIMESPEC "TS_clk" = PERIOD "clk" 0.025 us;
Good luck,
Hans
If you have synthesised under ISE, you can look at the command log file for examples; copy and paste these (modifying if necessary) to create your own script.
- Brian
Hi,
You can use Tcl script.
ISE10.1 can generate it for you : "Tcl Script Generation: Project Navigator can generate a Tcl script that contains all the necessary Tcl commands to create, modify, and implement your project from a Tcl command prompt. To generate this script, select Project > Generate Tcl Script..."
See also
Regards
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