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DONE problems

Hi, I am having a problem with a design. When DONE cycle is set to 5 or 6 DONE pin never goes high. I have confirmed that the part is configuring by scoping the output from the DCM. The part is a 2S300E.

When I scope out the INIT line I find that after 280mS the INIT line returns to a High-Z state - I believe that this is interupting the state machine so causing the DONE pin not to go high.

If I set the DONE cycle to 1, 2, 3 or 4 - DONE goes high and INIT stays high.

Any help would be appreciated

Dave

Reply to
ddallen
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What mode are you using to program the part? Is your configuration clock continuing to run at the end of configuration? Often stopping the clock too soon is the cause of this sort of problem.

HTH, Gabor

Reply to
Gabor

Dave,

I often find this with Spartan 2 designs. I am currently using the Digilent parallel port programmer but have seen identical problems with the Xilinx parallel port programmer. It seems to be pattern dependent in that it depends on the previously programmed configuration of the part. I have always managed to program the FPGA by first erasing the configuration prom, forcing a reconfiguration and then configuring the FPGA.

It does not affect programming of the configuration prom and I also haven't seen the problem on Virtex 2 designs.

kevin

Reply to
kevin

Hi Gabor, I am using slave Parallel mode and a fre running 33MHz clock

Dave

Reply to
Dave

Hi Kevin, Thanks for getting back to me - this sounds very promising. Do you have any more detail on the problem?

Dave

Reply to
Dave

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