Done Pin Remains Low after JTAG Configuration of V2Pro

If the done lines are wired in parallel then any un-configured device will drive DONE low. Probably a bit late now but it is always worth putting a jumper or zero ohm resistor from each of the FPGAs DONE connections so that you can isolate them individually if you need to.

John Adair Enterpoint Ltd.

This message is the personal opinion of the sender and not that necessarily that of Enterpoint Ltd.. Readers should make their own evaluation of the facts. No responsibility for error or inaccuracy is accepted.

Did you set the configuration startup clock to the JTAG clock (versus the default value, which is CCLK?)

Eric

Adarsh Kumar Ja>

Try using a pullup for HALTNEG and TRSTNEG in xilinx constraints editor tool Ram

Thanks for your suggestions. We are able to get something out from the Transceivers. I was using the JTAGClk and John, as you said, too late. The board was already designed ! I found another issue with ISE. It was ignoring some of my pin assignments without giving me any warnings or errors. Particularly, when i do not instantiate a differential clk buffer for an incoming differential clk (i was trying to get both the P and N out directly, just to check), the tool was assigning those pins to some dummy outputs i have just for simulation and debugging. And these outputs were basically smashing the incoming clk signal. Is this an issue with ISE or I was doing sthg fundamentally wrong ? Thanks Adarsh

tool

remain

Did you try "Enable Internal Done Pipe" in the startup options? It would seem that otherwise the device waits for the Done pin to go high.

Another approach I've used with a similar setup (except V2, not V2pro) is to generate a dummy project to load into each of the "unused" parts in the chain. When all parts are loaded, the Done pin should go high.