"don't cares" on ibuf output

Hello all :)

I'm doing back annotated simulation in ModelSim 5.6e with at94k_ver library(Atmel AT94K FPSLIC). Clock signals can't pass through the input buffers, the output of the ibuf module is "don't care" in ModelSim waveform viewer...Clock frequency is below the design's maximum frequency. Can anybody tell me what's wrong?

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veri-logic
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