Does Xilinx XST synthesize combinational divider?

I wrote a simple VHDL code using divide function. In Quartus II, it work fine. A LPM divider was synthesized. However, same code in ISE, a error " Operator must have constant operands or first operand must be power of 2" was given.

Does it mean XST is not able to synthesize combinational divider? Thanks

library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all;

ENTITY divider IS PORT ( op1, op2: IN STD_LOGIC_VECTOR( 7 DOWNTO 0 ); result : OUT STD_LOGIC_vector (7 downto 0) ); END divider;

architecture rtl of divider is begin result

Reply to
jasonL
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Most synthesizers only support factor of 2 division. The XST manual (page

479) states that arithmetic division is supported only for powers of 2

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The FPGA hardware needed to implement dividers is pretty slow so I wouldn't recommend just trying to have your code produce an LPM divider without understanding the delays you're going to experience. Also, the input/output sizes and known numerator limits relative to the denominator can

*significantly* reduce the amount of logic needed.

Dividers should be pretty easy to implement and should be optimized to your data flow for best results. If you have a specific implementation, I can rework an excel spreadsheet to show you how the data would flow with a fixed structure. You'd need to send me directly what your input sizes are and your desired output size along with the range of the numerator relative to the denominator; full (0->2^n-1)/(1->2^m-1) is much worse than if the numerator is always less than the denominator (or some fixed factor thereof). Also, signed versus unsigned is important for both factors. The Egyptian Division algorithm implemented in the spreadsheet lends itself directly to binary making the implementation simpler than the equivalent grade-school long division. I developed a nice pipelined best-fit divider (in my opinion) for a specific need in an ASIC-to-FPGA project algorithm conversion.

- John_H

Reply to
John_H

Hmm. It depends. I am annoyed that in XST for a two bit combinational divider I cannot write a

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comp.arch.fpga

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