Hi
I just wanted to know if people use systemc in FPGA flow. systemc can be used for cycle accurate simulation, where it can replace RTL. In this mode test-benches will usually take advantage of c++ and SCV (for writing constraints).
For big designs where RTL completion takes a lot of time systemc can be used for LT or AT simulations ( Loosely Timed, Approximately Timed TLM).
Pini
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Are you asking a question or pushing an advertisement? I doubt there are many on the group who don't know what SystemC is.
Proper capitalization may help -- "systemc" looks like a misspelling of "systemic". SystemC looks like -- well, SystemC.
-- Tim Wescott Wescott Design Services http://www.wescottdesign.com
The OP might be interested in this:
It's a verification paper, but the design flow was also in SystemC,
regards Alan
-- Alan Fitch
I am wondering what has SystemC got to do with FPGA design flow. If you are asking about support for synthesizable subset of SystemC , Xilinx and Alte ra do not support it in their FPGA flows (Quartus, ISE and Vivado). But it is supported in Vivado HLS. If you use HLS for FPGA designs, then yes, you can use SystemC directly. Of course, even outside of HLS, one can use Syste mC...depends on how many different models of our design we want to make.
I am currently using SystemC to model a memory hierarchy that will later be used on FPGAs. At this point it is a TLM model so it's pretty abstract. St ill have not decided if I will try to refine to RTL with SystemC or jump di rectly to VHDL once the behavior is validated.
However, I am also curious about how often people use it for FPGA design, i f it is worth it.
Cheers,
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