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Do I need to adjust sdram clk shift when i lower my system clock?

Hi everyon, hope someone can give me a pointer or help.

I lowered the system clock in the Altera stratix example design (standard) from 50 to 35 Mhz. Is it necessary to change the time shift of the sdram clock?? (-3.5ns by default)

because, a time shift of -3.5 ns seems to work fine until i fixed a huge (around 10k LE) jpeg decompression unit on to the system. Does anyone know do i need a new time shift or not? I tried a several delay from -1.0 to -8ns, but the system is still not stable, my c program can be downloaded to the board but at times fails to verification.

(It sometimes passes verification, but the program doesn't run properly. To simplify debugging, I only put a printf statment in my main(), but it doesn't print)

ps. I put my program and all data memory in sdram Thanks

Reply to
Tony
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When adding a huge amount of switching logic to any design, errors are very likely introduced by either placement or power supply droop. If you have any unconstrained paths, the large addition can create problems. However it is also likely that the additional power draw of the jpeg decompression is causing issues. I would recommend putting a scope on the power to make sure you're not getting a significant voltage drop due to the increased switching.

Also when reducing the SDRAM clock, make sure you don't violate the refresh period requirements. Normally refresh timing is done by counting clock cycles, but the parts require refresh periods that are not clock rate dependent, so you would need to reduce the number of cycles between refreshes by the ratio of the clock rate reduction.

HTH, Gabor

Reply to
Gabor

Hi Gabor, Thank you for your prompt reply. I am using Altera Stratix development board (pro edition 1s40) for this project. The board provide around 40k of LEs, and my whole design is only taking 15k of all. Do you think it's likely there is a power supply drop ? (by the way I am not sure how to check if there is power drop or not. :P )

I looked up the default timing setting for my sdram controller (I build my design based on the example design provided by Altera) in SOPC builder and all timing are specified in seconds except the "initialisation refresh cycles". Since cycle period increase when the frequency is lowered, the timing setting in seconds will end up the same no matter how I change the clock frequency?.

Thank you Tony

Reply to
Tony

Hi Tony,

At the end of this chapter there is some information on your question:

SDRAM Controller Core with Avalon Interface Datasheet:

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Good luck,

Karl.

Reply to
Karl

Hi Karl, I have already got the document and tried the estimation calculation, but the delay shift I worked out with the th, tsu and tco's which I got from my compilation report is quite different to the one (-3.35) demonstrated in the example calculation.

(I compiled the example standard design from altera and used the figures in the compilation report for calculation just in case some of my custom components affect the sdram timing ). In the compilation report, the tco's (max and min) I found are similar to the ones used in the example calculation , but the th and tsu I got are quite different .

What I did is, I looked into the sections "th" and "tsu" under the timing analysis report and find the largest possible th and tsu I could find that are related to sdram. Is this right ?

What I have been doing now is trial and error , and from that I am pretty sure the delay for my sdram should be around -3.5ns. But somehow its still not stable, I tried some printf statement trying to print data from the sdram and the program always stuck after printing the second character of all the character i wanted to print out.

Thank you very much , Tony

Reply to
Tony

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