Hi, I have been trying to make an example work in the DK Design Suite but to no avail. Can anyone who has experience in DK help me? The example is listed under Celoxica\DK\Examples\VHDL\Examples2 and it is one of the example listed in the help file which teaches how to interface handel c with vhdl code. The example can be found by search "vhd" under the celoxica help. However after I compiled the example into an edf file, and try generate the .bit file under Xilinx 7.1 the following error message appears: ERROR:NgdBuild:604 - logical block 'B121_reg32x1k_test_hcc_39_main_registers'
with type 'REG32X1K' could not be resolved. A pin name misspelling can cause
this, a missing edif or ngc file, or the misspelling of a type name. Symbol
'REG32X1K' is not supported in target 'spartan2'.
NGDBUILD Design Results Summary:
Number of errors: 1
Number of warnings: 0
It seems as if the vhd file component REG32X1K isn't detected. One of the examples in the help file says
To synthesize the VHDL, Verilog or EDIF integration examples, you must:
1.. Change the build configuration to EDIF, VHDL or Verilog as appropriate (Build>Set Active Configuration). 2.. For Verilog or VHDL examples, choose the HDL output style: select Project>Settings>Linker, and then chose an output style from the drop-down list. Choose the style that matches your RTL synthesis tool, or else choose Generic. 3.. For Verilog or VHDL examples, pass the DK-generated .v or .vhd files, the .v or .vhd example files (tt17446, reg32xlk or filter/wrapper) and the Handel-C support file (HandelC.v or HandelC.vhd) to your synthesis tool. If you are targeting a Xilinx platform you also need to pass the appropriate ROC file (xilroc.v or xilroc.vhd). 4.. Run place and route. However, I am unable to find any handelc.vhd or xilrox.vhd anywhere in the celoxica directory. Is there anything else I need to do to make this work? Thanks a lot.