Discrepancy in CLB Usage Report

Hi,

I am using the following flow:

VHDL - Entry Synplify Pro - Synthesis Xilinx Design Manager - Post synthesis, place and route, etc.

The target device is Xilinx Spartan XL - XCS20XL.

I am trying to understand the two summaries:

1. Synthesis Summary -------------------- Logic Mapping Summary: FMAPs: 243 of 392 (62%) HMAPs: 83 of 196 (43%) Total packed CLBs: 173 of 196 (89%)