All, I've got some directed routing constraints in my UCF file. After some recent changes I get the following message in the P&R PAR file:-
# of EXACT MODE DIRECTED ROUTING found:14, SUCCESS:9, FAILED:5
Anyone know how to find out which nets are failing? I can't find anything in the report files.
TIA, Syms.
If you have access to ISE 8.1, you can use FPGA_EDITOR to find out which DIRTs failed.
HTH, Jim
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Hi Jim, Thanks. That's what I have to do with 7.1. Go through each net looking for the failures. I vainly hoped that, as it knows some nets have failed, the tool might have the common courtesy to tell me which ones. No. Cheers, Syms.
As I said, you need to have acess to ISE 8.1 (note the version number). In FED 8.1, you can select "Directed Routing Nets" from the List window. It then shows all the directed rounting nets in the ncd and their status (Type. Matched, etc).
HTH, Jim
All right, I did get that mate!! ;-)
Aha, now I see what you're saying, there's a new feature! Cool, I'll try it, even though it goes against my principle of waiting for SP3!
Sure does, many thanks!
Any wagers whether they've changed the #@%$&!! pan & zoom functions (again) in FPGA editor 8.x ?
Also, for other 7.1i FPGA Editor "features", see Answer Records
22469, 21667, and 22217 ( loss of config info on manual comp edits )Brian
Hi Brian, So that's interesting. It's getting to the point where I no longer trust the FPGA editor to do anything useful. I think the directed routing feature is used by a lot of Xilinx's own IP developers so it has a fighting chance of being OK! Whatever happened to those great days of the 3000 series and XACT? yours cynically, Syms. p.s. For some reason I missed the 'PCI compliance' thread a couple of weeks back. Still, I was lol when I read it yesterday! Thanks!
A little nostalgic bug reporting:
Back in the good old days, I entered designs directly in XACT and simulated the lca file using ViewSim.
The last versions of XACT had a very annoying bug, where occasionally a seemingly random CLB in the design would be wiped out; you'd have to go back and re-create the logic each time this happened.
I finally caught on that the problem only occured when you had done an EditBlock, followed by a SWItch, and then done a process like DRC that shelled out, without first doing an ENDBLOCK.
Once I started closing any open blocks first, the problem vanished, never to return; and the designers rejoiced.
Brian
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