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Digital Tachometer VHDL

Hi,

I have this project where I have to design a tachometer using VHDL. The thing is I m pretty new to the field of electronic projects and I m very new to VHDL.

The project asks me to count the Rotations/per Minute from a motor. It has to be in the range 19-98 RPM, the measurement time is 1.1s, and the display resolution is 0.1 .

The good part is that I dont have to create a system to get this rotations, they are given to me thru a generator. I just have to count the pulses and display the result.

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So, I tought I'll use an AND gate with the signal from the general as one input and the clock divided so I'll obtain the period of 1.1s . [url]
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What I have to do next is when i press a button it will count the pulses for 1.1s and then display the result. [During counting the display will be OFF].

Sorry for the long post but the first problem resumes to this. How do i design a clock divider so I can get a period of 1.1s.

I have a basic clock divider code where i count the rising edges and then i change the state of clock. But how many edges i have to count?

So : How do i get a clock with 0.909 freqvency from 50 MHZ internal clock of fpga?

[code]ENTITY CLKDIV IS PORT( CLK: IN STD_LOGIC; CLKOUT: OUT STD_LOGIC ); END CLKDIV;

ARCHITECTURE DIV OF CLKDIV IS BEGIN PROCESS (CLK) VARIABLE COUNT: INTEGER RANGE 0 TO ???? :=0; VARIABLE STATE: STD_LOGIC := '1'; BEGIN IF(RISING_EDGE (CLK)) THEN IF(COUNT= )THEN COUNT:=0; STATE:= '1'; ELSE COUNT := COUNT+1; END IF; IF(COUNT=) STATE:= NOT STATE; END IF; END IF; CLKOUT

Reply to
tachometer
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Many years ago (in the TTL days, likely before microprocessors) there was a digital tachometer design in an electronics magazine.

To get a reasonable update rate, they used a PLL frequency multiplier.

If you want 1RPM resolution, you would otherwise have to count for one minute, and for 0.1RMS for 10 minutes. That is a little slow if someone wants to use it to adjust the speed.

With a PLL frequency multiplier, if it can lock you can get an accurate RPM much sooner.

-- glen

Reply to
glen herrmannsfeldt

I won't tell the solution, because it might be part of the homework, but assuming no jitter on the input signal and a 50 MHz clock in the FPGA, it is no problem at all to measure it with 0.1 RPM resolution, and even better. Of course, measuring 19 RPM in 1.1 second is impossible with a single measurement cycle, if the motor gives one impulse per rotation. Maybe it should be the update rate of the display?

--
Frank Buss, http://www.frank-buss.de
electronics and more: http://www.youtube.com/user/frankbuss
Reply to
Frank Buss

So think about what you've just said -- if there's sufficient information to do it with a PLL, doesn't that mean there's sufficient information in the incoming signal? And what might that sufficient information be?

(Sorry about being so mystical -- this has _got_ to be a student project, and while I'm perfectly willing to help, I'm not going to just throw answers away. Hence, Socrates).

--
Tim Wescott
Control system and signal processing consulting
www.wescottdesign.com
Reply to
Tim Wescott

e

I don't mind giving more obvious hints...

period =3D 1/freq

Rick

Reply to
rickman

Hmmm... Measuring period within 1.1 seconds limits us to a minimum RPM of 54.5454 assuming one pulse per revolution from the motor. That can give a clue as to how many PPR - pulses per revoultion - would be needed to resolve to the minimum RPM stated.

--

Michael Karas
Carousel Design Solutions
http://www.carousel-design.com
Reply to
Michael Karas

Missing here is how many pulses per revolution ?

If it is one, how many pulses will you get in 1.1s, at 19 rpm ? If it is >>1, how many PPR do you need to resolve 0.1rpm, in 1.1sec ?

Also google Reciprocal frequency counting.

You have been given a relatively low resolution of 0.1, which is only 99.9 FSV, so a smart student will spot that only 999 entries in a table, to give RPM direct from any scaled time.

Does your target hardware support tables ? (ie initialized RAM )

Is the display 3x7 segment LED ? [19-98 is fixed decimal]

-jg

Reply to
j.m.granville

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