Digital Filter and external PLL (VCO)

axalay schrieb:

The loop filter of a PLL/DLL may help here. So you'd build a "analog" PLL with only a phasecomparator+loopfilter and a VCO. How is the jitter spectrally distributed ? Design the loop filter appropriately. Doing it completely in the FPGA may also work, but is limited by the maximum clock you can do to maybe >1ns jitter with a "multiphase clock design" or similar.

The 1 Up/Down charge pump seems simpler and has the advanteage of the only sidebands (Fref 8KHz)proportional to phase difference(jitter).

For 2 the PWM frequency should be high enough compared to the loop frequency (

I am generate 2.048 MGz from (19.44 * 8) MGz so:

//=CC=EE=E4=F3=EB=FC =F4=EE=F0=EC=E8=F0=F3=E5=F2 =E8=E7 155.52 =CC=C3=F6 8.=

192 =CC=C3=F6 //=C4=EB=FF =FD=F2=EE=E3=EE =ED=E5=EE=E1=F5=EE=E4=E8=EC=EE =E2=FB=E4=E0=F2= =FC 126 =F0=E0=E7 10 =EF=E5=F0=E8=EE=E4=EE=E2 =E8 130 =F0=E0=E7 9 =EF=E5=F0=E8=EE=E4=EE=E2 //4 =EB=E8=F8=ED=E8=F5 9 =EF=E5=F0=E8=EE=E4=EE=E2 =E2=FB=E4=E0=E5=EC =ED=E0= 1-=E9, 64-=E9, 128-=E9 =E8 193-=E9 =F0=E0=E7=FB module divide_clk (RESET, iCLK, oCLK); input RESET; input iCLK;

output oCLK; reg oCLK;

reg [7:0] aCOUNT; //=D1=F7=E5=F2=F7=E8=EA reg [4:0] bCOUNT; //=D1=F7=E5=F2=F7=E8=EA =E8=ED=F2=E5=F0=E2=E0=EB=E0 9 = =E8=EB=E8 10 CLK

always @(posedge iCLK) begin if (!RESET) begin oCLK =3D 0; aCOUNT =3D 0; bCOUNT =3D 0; end //if else begin if (aCOUNT =3D 128 && aCOUNT

"""Peter Alfke ÐÉÓÁÌ(Á): """

I do SDH (STM1-STM16) synchronization circuit. :) and sorry for my bad english