Digital clock synthesis

bit?

You can have either a separate adder or (as I did it before) two different phase values supplied by software: the raw phase and the adjusted phase. If you want an adder to calculate the adjusted phase value, register the value and the timing doesn't suffer.

Just a reminder that the duty cycle will be (2^26/100M)/(1-2^26/100M) or

67.1%/32.9% on average unless you'd care to adjust whenever the MSbit toggles.
Reply to
John_H
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Why not use a xtal with a power of two frequency?? We telecom guys do this regulary.

Regards Falk

Reply to
Falk Brunner

Ray -

I agree for a general-purpose synthesizer with a phase accumulator addressing a SINE look-up table. But if you don't need a general-purpose synthesizer (i.e., you only need to generate one output frequency) then can't you pick any modulus you need and create the SINE LUT to match that modulus?

And if you just need a digital (1-bit) output clock then you should always be able to pick whatever accumulator modulus you want and use the MS bit of the accumulator as the output clock. The only requirements are that Fout = Fin * (M/N), where M and N are both integers and M/N

Reply to
RobJ

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Unless you are dealing with an application that needs a frequency tolerance of +/- less than 1 Hertz, a 27 bit accumalator and a 100 MHz clock is quite fine. It is rare in consumer or most industrial electronics that the frequency generated need be that tight of tolerance. Even if so then pick a value for your accumalator and match the crystal that will give you 1 Hz steps.

james

Reply to
james

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