Digesting runs of ones or zeros "well"

The implementation can, indeed, be as you imagine. No nagging necessary. Your earlier pseudocode did just what you're suggesting here. One of the reasons I went with the MUXF5 was that the primitive doesn't need the syn_keeps that I use to coerce the synthesis into thinking how I want; a LUT savings is nice though at a slight cost in delay if I want the combinatorial output. But your discussion makes me wonder if the Xilinx AND3 primitive will work just as well. I'll test it out when I get back to work. Comparing the implementations below, the only advantage to "mine" is one fewer LUT.

Maybe the synthesizer will let this stay. I don't have to define intermediate variables to syn_keep and I don't need nested loops. Since I don't need to use the xnors, I don't even need to comment the code any more than usual.

generate for( h=0; h

Sorry. I wasn't trying to be an asshole.

I thought you were into trying to partitioning logic into LUTs in some sneaky way.

I assumed software is smart enough to compute an INIT string from a logic equation. The old Xilinx tools could do that for

3000 series parts. Has that fallen through the cracks with the newer software?

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If I'm manually instantiating LUTs, the Synplify synthesizer has nothing to base the INIT upon: no equations, no clue. If I manage to convince the software to get into the LUTs that I need so I can go into the EDIF netlist (or HDL Analyst) and find the INITs, I've already achieved my goal of getting the design into teh desired LUTs. If I do get the INITs from those sources, I must be absolutely sure I get the port order correct or the logic is blown (or I need to do the ol' Carnot shuffle).

I tried to instantiate a LUT the other day and I couldn't figure out the "right" way to do the Verilog for Synplify since there are INIT parameters for simulation and xc_props="INIT=xxxx" for synthesis as far as I can tell. I had something that looked un-LUT-like in the HDL Analyst technology viewer so I didn't pursue that furhter.

Code with LUTs and INITs is sincerely less supportable than code with something as annoying as an AND3 primitive instantiation. Interesting thing with the AND3 - there was no primitive in the virtex2.v file included in the Synplify flow but a quick black_box definition in my source and the synthesizer knew it was a 3-input AND. It implemented in the Xilinx device just fine.

Oh - Vinh, if you're reading... I used an inference of the form

bytesPlus1[8:1]==bytesPlus1[7:0]

and got a note in Synplify saying it "detected a comparator ==" and produced your two-levels of logic with the 4-input AND. If you do things "just" the right way.... Oy.

This seems like a good addition to the tools discussion in other threads.

There really should be a simple way to say something like: Generate this signal in a LUT (or whatever) with these inputs. Possibly constraining the location and/or locking some inputs to particular ports. The idea is that the system will figure out the details from the info it already has.

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Hi,

The way I use to do it is to draw a carnaugh map and include it in a comment above the instanciated lut.

Göran

John_H wrote:

Great John :_) Glad you found a compact way of getting Synplify to do what you want. It's a great synthesizer, but like all of them, it's got it's own quirky "dialect." Good ol' trial and error.

Heh one annoying situation is when the synthesizer "optimizes" 90% of your design away, and you have to hunt down that little itty bitty bit of code that caused it.

"John_H" skrev i melding news:Xwoeb.26$ snipped-for-privacy@news-west.eli.net...

9

I just started reading this thread.. Am I correct if you really want to detect 9 EQUAL bits in a row from a stream? Could you not do this just with a 4bits counter and a comparator/zero detector?

Not unless you're building a heat engine out of your FPGA...

Homann

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You can look at nibbles without the smear. If you know that all bits in each of the nibbles are equal you can select one bit for each nibble as a representant and check whether the nibbles are equal.

for each byte: eq3210

Correct, I need "equal" bits, either 9'h000 or 9'h1ff, starting from

0, 8, 16, ... 56.

The input is 65 bits per clock with a fast clock, output from BlockRAM which was loaded at full width.

Counters require more than one clock.

Just goes to show how little my Karnaugh skills are used.

Thanks for the laugh. :-)

I was trying to underscore that nibble checks with the 9th bit as the qualifier were not sufficient. You expand upon this below by qualifying with the [0] and [4] bits from the nibbles you looked at.

I appreciate the fresh perspective - I tried coding some things inline similar to what you suggested, all with sub-optimal results. Using syn_keeps on the three different variables and ANDing them together would produce a valid result much like what has been achieved already. It's too bad the nibble approach didn't convince the synthesizer to do things any different than before.

You can do it, and it is fairly simple. The shortcut method is to partition the logic by using keep buffers (syn_keep attributes in synplify). The synthesizer will preserve the signals with the keep buffer, which pushes those signals onto LUT outputs. The lut contents are then specified with logic equations and the luts are inferred. For example:

attribute syn_keep of d:signal is true; attribute syn_keep of h: signal is true;

begin

d

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I'm not sure I caught your requirement completely. As I understand it, you need to detect when there are 9 0's or 9 1's starting at a byte boundary? That can be done with a bit of logic and a carry chain:

the lsb inverts the remaining bits if it is zero, otherwise the remaining bits are passed to the carry chain unchanged. the carry chain gets the conditionally inverted bits starting at LSB+1, and at the 9th bit you look at the carry chain output (the carry in at the base of the chain is also a '1'). If all the bits match the LSB, you get a '1' on the carry chain output. This is easiest to code with instantiated MUXCY's rather than pushing on a rope to get the synthesizer to figure out you want to use the carry chain as a wide and gate. Not sure if this meets your requirement or not, but it is illustrative of how you might tackle a similar problem with a perhaps less than obvious approach.

John_H wrote:

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Like this one? I rememebred seeing this mentioned a few weeks ago - a quick google and I found a link to it... from andraka.com of all places :-) [ Ray, you might want to update the link ]

Scroll down to "Locking Logic to a Single Xilinx Virtex LUT"

Cheers, Martin

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Followup to: By author: Ray Andraka In newsgroup: comp.arch.fpga

placement.

which

Here is a simple Perl script that produces the appropriate LUT bit pattern for a 4-input LUT given any arbitrary boolean expression involving "0", "1", "a", "b", "c", "d". The operators are the stanard C/Perl ~ | ^ & -- the booleanizing operators including ?: and ! should not be used. The extension to 5-input LUTs should be obvious.

This should be easily tweakable to produce any particular syntax desired.

Posted mostly as an example.

-hpa

#!/usr/bin/perl

$e = join(' ', @ARGV); $e =~ s/1/\(\$one\)/g; $e =~ s/a/\(\$a\)/g; $e =~ s/b/\(\$b\)/g; $e =~ s/c/\(\$c\)/g; $e =~ s/d/\(\$d\)/g;

$one = 0xffff; $a = 0xaaaa; $b = 0xcccc; $c = 0xf0f0; $d = 0xff00;

printf "%04x\n", eval($e) & $one;

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placement.

which

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