John
Pushing rope is a good analogy. Jan Gray, yeah?
When writing HDL, on one extreme you can write your code to explicity tell the synthesizer how to structure your logic. You'd instantiate logic primitives and wire them all up. You're basically doing all the work for the synthesizer. The benefit is total control. The problem is a lot of code to write, which means increase chances of human error and a lot of rewriting when you make changes to your design.
On the other extreme, you have code that's structureless. You imply no logic or wiring inside. It's purely a black box and leaves it up to the synthesizer to figure things out. The benefits are more compact code and "ease" of modification (if your algorithm isn't too convoluted). The problem of course is the synthesizer usually doesn't do exactly what you want. Much like a 2 year old coming up to you with a smile full of pride saying, "I went potty!" only to realize they did it on the floor.
So when the synthesizer isn't smart enough, you need to help it out by putting a little more structure into your code. Basically you're giving the synthesizer hints on what you want. Also hardware engineers tend to better understand algorithms that have a bit of hardware structure to them. We once had a math major write VHDL, and the comment from one engineer was, "Man, his code looks like C." :_D
Unfortunately I don't use Verilog, but hopefully some psuedo code will be enough to give you an idea of what I'm thinking.
I noticed your code was bit based. Since you only are checking on byte boundaries, it can help to write your code byte based. Good luck with this psuedo code (you should see my C).
data[64:0] -- 65-bit input data signal eight_0s_consec_flag[7:0] -- intermediate signals eight_1s_consec_flag[7:0] -- intermediate signals ninth_bit[7:0] -- intermediate signals consec_detect_flag[7:0] -- 8-bit output signal
for byte = 0...7
lsb = byte*8 msb = byte*8+7
if data[msb:lsb] = "00000000" then eight_0s_consec_flag[byte] = '1' else eight_0s_consec_flag[byte] = '0' end if
if data[msb:lsb] = "111111111" then eight_1s_consec_flag[byte] = '1' else eight_1s_consec_flag[byte] = '0' end if
ninth_bit[byte] = data[msb+1]
if ninth_bit[byte] = '1' then consec_detect_flag[byte] = eight_1s_consec_flag else consec_detect_flag[byte] = eight_0s_consec_flag end if;
end loop
Well hopefully that's correct, and makes sense. Let me know if you have any questions or see any problems.
Regards, Vinh